Testing system for testing semiconductor package stacking chips and semiconductor automatic tester thereof

Patent metadata

Field	Value
Publication number	US-9250292-B2
Application number	US-201313854372-A
Country	US
Kind code	B2
Filing date	Apr 1, 2013
Priority date	May 3, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A testing system for testing semiconductor package stacking chips is disclosed. The system includes a testing socket, a testing arm, and a testing mechanism. The testing mechanism includes a probe testing device. The probe testing device has a testing chip inside and a plurality of testing probes electrically connected to the testing chip. The plurality of testing probes extends toward the testing socket for contacting a chip-under-test loaded on the testing socket. When the testing mechanism moves to an upper position between the testing socket and the testing arm, the testing arm moves downward in the vertical direction and presses down the testing mechanism thereby coercing the plurality of testing probes in the testing mechanism to closely abut against the chip-under-test, so that the testing chip inside the testing mechanism can electrically connect to the chip-under-test for forming a test loop.

First claim

What is claimed is:

1. A testing system for testing semiconductor package stacking chips, comprising:
a testing socket for loading a chip-under-test;
a testing arm installed over the testing socket, for moving in the vertical direction; and
a testing mechanism for moving to an upper position over the testing socket and leaving the upper position, the testing mechanism comprising a probe testing device, the probe testing device having a testing chip inside and a plurality of testing probes electrically connected to the testing chip, the plurality of testing probes extending toward the testing socket for contacting the chip-under-test loaded on the testing socket;
wherein when the testing mechanism moves to the upper position between the testing socket and the testing arm, the testing arm moves downward in the vertical direction and presses down the testing mechanism thereby coercing the plurality of testing probes in the testing mechanism to closely abut against the chip-under-test, so that the testing chip inside the testing mechanism is electrically connected to the chip-under-test for forming a test loop; and
wherein the testing mechanism is physically unattached to and independent from the testing arm, such that the moving of the testing mechanism to the upper position or leaving the upper position is independent from the moving of the testing arm in the vertical direction.

2. The testing system according to claim 1 , wherein the testing mechanism comprises a frame and an elastic element, wherein the elastic element is connected across the probe testing device for restoring the probe testing device after completing the test.

3. The testing system according to claim 1 , wherein the testing mechanism moves to the upper position over the testing socket and leaving the upper position back and forth by means of a set of tracks.

4. The testing system according to claim 1 , wherein the probe testing device of the testing mechanism further comprises a load board and a probe interface, wherein the testing chip is inserted in the load board and electrically connected to the probe interface.

5. The testing system according to claim 1 , wherein when the testing mechanism is at the upper position and the testing arm moves upward in the vertical direction, the testing mechanism is physically separated from the testing arm and is free to leave the upper position.

6. A semiconductor automatic tester for testing package stacking chips, comprising:
a testing area configuring a test board having a testing socket for loading a chip-under-test;
a charging area configuring a tray for loading the chip-under-test of waiting the test;
a discharging area configuring a tray for loading the chip-under-test of completing the test;
a pick-up arm for moving the chip-under-test loaded on the tray in the charging area, on the tray in the discharging area and on the socket in the testing area;
a testing arm located over the testing socket for moving in the vertical direction; and
a testing mechanism for moving to an upper position over the testing socket and leaving the upper position, the testing mechanism comprising a probe testing device having a testing chip inside and a plurality of testing probes electrically connected to the testing chip, the plurality of testing probes extending toward the testing socket for contacting the chip-under-test loaded on the testing socket;
wherein when the pick-up arm moves the chip-under-test from the tray in the charging area to the testing area, the testing arm moves the chip-under-test to the testing socket of the test board, and when the testing mechanism moves to the upper position between the testing socket and the testing arm, the testing arm moves downward in the vertical direction and presses down the testing mechanism thereby coercing the plurality of testing probes in the testing mechanism to closely abut against the chip-under-test, so that the testing chip inside the testing mechanism is electrically connected to the chip-under-test for forming a test loop, and then the pick-up arm moves the chip-under-test of completing the test to the tray in the discharging area; and
wherein the testing mechanism is physically unattached to and independent from the testing arm, such that the moving of the testing mechanism to the upper position or leaving the upper position is independent from the moving of the testing arm in the vertical direction, and when the testing mechanism is at the upper position and the testing arm moves upward in the vertical direction, the testing mechanism is physically separated from the testing arm and is free to leave the upper position.

7. The semiconductor automatic tester according to claim 6 , further comprising a load socket for loading the chip-under-test, the load socket moving to a lower position under the testing arm and leaving the lower position, so that the testing arm is capable of moving the chip-under-test to the testing socket.

8. The semiconductor automatic tester according to claim 6 , wherein the testing mechanism comprises a frame and an elastic element, wherein the elastic element is connected across the probe testing device for restoring the probe testing device after completing the test.

9. The semiconductor automatic tester according to claim 6 , wherein the testing mechanism moves to the upper position over the testing socket and leaving the upper position back and forth by means of a set of tracks.

10. The semiconductor automatic tester according to claim 6 , wherein the probe testing device of the testing mechanism further comprises a load board and a probe interface, wherein the testing chip is inserted in the load board and electrically connected to the probe interface.

11. The semiconductor automatic tester according to claim 6 , wherein when the testing mechanism is at the upper position and the testing arm moves upward in the vertical direction, the testing mechanism is physically separated from the testing arm and is free to leave the upper position.

Assignees

• Chroma Ate Inc

Inventors

• Chen Chien-Ming

Classifications

• G01R31/2896 Primary

  Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

• G01R31/2887

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title