Embedded die packaging for power semiconductor devices

Patent metadata

Field	Value
Publication number	US-11342248-B2
Application number	US-202016928305-A
Country	US
Kind code	B2
Filing date	Jul 14, 2020
Priority date	Jul 14, 2020
Publication date	May 24, 2022
Grant date	May 24, 2022

Abstract

Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

First claim

The invention claimed is:

1. An embedded die package comprising a laminated body and a die comprising a power semiconductor device, embedded within the laminated body, wherein:
the die comprises a patterned layer of conductive metallization on a front-side of the die providing first and second contact areas of the semiconductor power device, and a thermal contact area on a back-side of the die; and
a layer stack of the laminated body comprises:
a core comprising at least one dielectric layer which embeds the die;
a first dielectric build-up layer on a first side of the core;
a first conductive layer on the first dielectric build-up layer;
the first conductive layer being patterned to define first and second interconnect areas;
the first and second interconnect areas of the first conductive layer being connected by electrically conductive vias to respective first and second contact areas on the die; and
an outer dielectric build-up layer extending over the first dielectric build-up layer and first conductive layer,
the outer dielectric build-up layer laterally electrically isolating the first and second interconnect areas of the first conductive layer in a region extending over the die between said first and second interconnect areas and vertically separating said region from an external surface of the laminated body.

2. The embedded die package of claim 1 , wherein the power semiconductor device comprises one of:
a power transistor device comprising first and second load contacts and a control contact; and
a power diode device having first and second load contacts;
wherein said first and second contact areas comprise contact areas for any two of said contacts.

3. The embedded die package of claim 2 , wherein:
the power semiconductor device comprises a power semiconductor transistor device, and said first and second load contacts and control contacts are referred to as any one of: source, drain and gate; emitter, collector and gate; emitter, collector and base; source, collector and gate;
anode, cathode and gate; and combinations thereof.

4. The embedded die package of claim 2 , wherein:
the power semiconductor device comprises a power semiconductor diode device and said first and second load contacts are anode and cathode.

5. The embedded die package of claim 1 , wherein the external surface comprises a coating of solder resist extending over the outer dielectric build-up layer, the coating of solder resist being isolated from the underlying first conductive layer by the outer dielectric build-up layer.

6. The embedded die package of claim 1 , wherein said at least one dielectric layer of the core and said first, second and outer dielectric build-up layers comprise any one of: a glass-fiber reinforced resin composition; a glass-fiber reinforced epoxy resin composition; a dielectric resin build-up layer; a dielectric epoxy build-up layer; a build-up layer which is formed from an ABF (Ajinimoto Build-up Film); and a combination thereof.

7. The embedded die package of claim 1 , wherein said conductive layers and conductive vias comprise copper.

8. The embedded die package of claim 1 , wherein the power semiconductor device comprises any one of:
at least one power transistor;
at least one power diode;
a combination of at least one power transistor and at least one power diode.

9. The embedded die package of claim 8 , wherein the power semiconductor device comprises a plurality of power transistors configured as one of a half-bridge, a full-bridge and other switching topologies.

10. The embedded die package of claim 8 , wherein the power semiconductor device is fabricated from any one of: GaN and other III-Nitride semiconductor materials; and Si, SiC and other Group IV materials.

11. The embedded die package of claim 1 , wherein the power semiconductor device comprises one or more of:
at least one lateral GaN transistor wherein said first and second contact areas of the power semiconductor device comprise source and drain contact areas of the lateral GaN power transistor;
at least one lateral GaN diode, wherein said first and second contact areas of the power semiconductor device comprise anode and cathode contact areas of the lateral GaN diode.

12. The embedded die package of claim 1 , wherein the power semiconductor device comprises at least one of a GaN HEMT, a GaN diode, a SiC MOSFET, a SiC diode, a Si IGBT, and a Si diode.

13. The embedded die package of claim 1 , wherein the power semiconductor device comprises at least one high voltage, high current lateral GaN HEMT rated for operation at ≥100V or ≥600V.

14. The embedded die package of claim 13 , wherein the at least one GaN HEMT is rated for operation at a temperature ≥75 C.

15. The embedded die package of claim 13 , wherein the at least one GaN HEMT is rated for operation at a temperature ≥100 C.

16. The embedded die package of claim 1 , wherein:
the die comprises at least one of: driver circuitry, control circuitry and other components integrated with the power semiconductor device.

17. The embedded die package of claim 1 , wherein the power semiconductor device is co-packaged with other components embedded in the layer stack.

18. An embedded die package comprising a laminated body and a die comprising a semiconductor power transistor embedded within the laminated body, wherein:
the die comprises a patterned layer of conductive metallization on a front-side of the die providing electrical contact areas for source, drain and gate of the semiconductor power transistor, and a thermal contact area on a back-side of the die; and
a layer stack of the laminated body comprises:
a core comprising at least one dielectric layer which embeds the die;
a first dielectric build-up layer on a first side of the core;
a first conductive layer on the first dielectric build-up layer;
a second dielectric build-up layer on a second side of the core;
a second conductive layer on the second dielectric build-up layer;
a third dielectric build-up layer on the first conductive layer;

the first conductive layer being patterned to define source, drain and gate interconnect areas;
the second conductive layer being patterned to define source, drain and gate interconnect areas and a thermal pad;
the source, drain and gate interconnect areas of the first conductive layer being connected by electrically conductive vias to respective source, drain and gate contact areas on the die;
the source, drain and gate interconnect areas of the first conductive layer being connected by electrically conductive vias to respective source, drain and gate interconnect areas of the second conductive layer;
the thermal pad of the second conductive layer being connected by thermal vias to the thermal contact area on the back-side of the die;
and
the third dielectric build-up layer extending over the first dielectric build-up layer and first conductive layer,
the third dielectric build-up layer laterally electrically isolating the source and drain interconnect areas of the first conductive layer in a region extending over the die between the source and drain interconnect areas and vertically separating said region from an external surface of the laminated body.

19. The embedded die package of claim 18 , comprising at least one of:
a coating of solder resist on the second build-up layer having openings to the source, drain and gate contact areas of the second conductive layer and the thermal pad of the second conductive layer; and
said external surface of the laminated body compri

Assignees

• Gan Systems Inc

Inventors

• Mcknight-Macneil Cameron
• Klowak Greg P

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/658 Primary

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title