Packaging solutions for devices and systems comprising lateral GaN power transistors

Patent metadata

Field	Value
Publication number	US-9589868-B2
Application number	US-201615064750-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 11, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

First claim

The invention claimed is:

1. A semiconductor device structure comprising an assembly of:
a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate;
the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
the leadframe comprising copper, or other metal or metal alloy, having high electrical conductivity and thermal conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of one side of the leadframe by low inductance connections to form an interposer sub-assembly;
source, drain and gate leads of the leadframe extending laterally and vertically from the GaN die to provide source, drain and gate contact surfaces, coplanar with the die-attach surface of the GaN die, for electrical interconnections to respective coplanar contact areas of the substrate; and
the die-attach between the back-side surface of the GaN die and the respective source, drain and gate interconnections comprising a layer of interconnect material which is electrically and thermally conductive.

2. The device of claim 1 , wherein the substrate comprises a ceramic substrate of a power module for thermal dissipation, the ceramic substrate being metallized on both sides to provide coplanar source, drain and gate contact areas on one side, and a die attach area on said one side being co-planar with said contact areas.

3. The device structure of claim 1 , wherein the substrate comprises a Printed Circuit Board (PCB) providing co-planar source, drain and gate contact areas and a die-attach area of the PCB which is coplanar with said contact areas, and wherein the die-attach area of the PCB provides for thermal dissipation.

4. The device structure of claim 1 , wherein the semiconductor substrate of the GaN die comprises a silicon substrate.

5. The device structure of claim 1 , wherein the semiconductor substrate of the GaN die comprises a silicon carbide substrate.

6. The device structure of claim 1 , wherein the low inductance connections comprise any one of:
a layer of sintered silver;
metal bump or post connections;
solder tipped copper pillars; and
a combination thereof.

7. The device structure of claim 1 , wherein the back surface of the GaN die is attached to the die-attach area of the substrate by sintered silver.

8. The device structure of claim 1 , wherein the back surface of the GaN die is attached to the die-attach area of the substrate by solder and the source, drain and gate interconnections from the leadframe to the substrate comprise solder.

9. The device structure of claim 1 , wherein the interposer sub-assembly comprises the GaN die and leadframe and further comprises a thermal dissipation layer.

10. The device structure of claim 9 , wherein the GaN die is attached to said one side of the leadframe and the thermal dissipation layer comprises a ceramic substrate attached to an opposite side of the leadframe.

11. The device structure of claim 10 , wherein the ceramic substrate supports a plurality of leadframe components providing individual source, drain and gate leads.

12. The device structure of claim 1 , further comprising a second lateral GaN die or other semiconductor die co-packaged and electrically interconnected with the said GaN die.

13. An interposer sub-assembly of a GaN die and a leadframe for the device structure of claim 1 , wherein the GaN die is electrically connected to contact areas on one side of the leadframe, and the leadframe provides source, drain and gate contact areas coplanar with a back-side die-attach surface of the GaN die.

14. An interposer sub-assembly of a GaN die, a leadframe and a thermal substrate, for the device structure of claim 1 , wherein the leadframe is sandwiched between the GaN die and the thermal substrate, the GaN die being electrically connected to contact areas on one side of the leadframe and the thermal substrate being bonded to an opposite side of the leadframe for thermal dissipation and the leadframe provides source, drain and gate contact areas coplanar with a back-side die-attach surface of the GaN die.

15. The interposer sub-assembly of claim 14 , wherein the leadframe comprises brazed copper and the thermal substrate comprises a ceramic thermal substrate bonded to the brazed copper leadframe, and the GaN die-attach is electrically and thermally bonded to the leadframe by a sintered silver layer.

16. The interposer sub-assembly of claim 15 , wherein a second thermal substrate is bonded to the back surface of the GaN die and the second thermal substrate provides said die-attach surface of the GaN die.

17. A method of fabricating a semiconductor device structure comprising an assembly of a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate, the method comprising:
providing the GaN die comprising, on a front surface thereof, source, drain and gate contact areas for the lateral GaN power transistor and a back surface thereof for die-attach;
providing the leadframe of copper, or another metal or metal alloy having a high electrical conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die;
attaching the source, drain and gate contact areas of the GaN die with electrical interconnections connected to respective source, drain and gate portions of one side of the copper leadframe, comprising low inductance bump or post connections, to form an interposer sub-assembly;
source, drain and gate leads of the leadframe extending laterally and vertically of the GaN die to provide source, drain and gate leads providing contact surfaces coplanar with the die-attach surface of the GaN die for electrical interconnection to respective coplanar contact areas of the substrate; and
providing a layer of soldered or sintered material which is electrically and thermally conductive to attach the back-side surface of the GaN die to the die-attach area of the substrate, and to electrically interconnect the respective source, drain and gate interconnections of the leadframe and substrate contact areas.

18. The method of claim 17 , comprising processing the bump or post connections and the attachment material to vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions.

19. The method of claim 17 , further comprising providing a package body comprising an over-molding of encapsulation.

Assignees

• Gan Systems Inc

Inventors

• Mcknight-Macneil Cameron
• Klowak Greg P
• Mizan Ahmad

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title