Asymmetric doherty power amplifiers
US-12176859-B2 · Dec 24, 2024 · US
US2016285418A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016285418-A1 |
| Application number | US-201514666999-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 24, 2015 |
| Priority date | Mar 24, 2015 |
| Publication date | Sep 29, 2016 |
| Grant date | — |
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An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.
Opening claim text (preview).
What is claimed is: 1 . An amplifier comprising: a semiconductor substrate having a top substrate surface and a bottom substrate surface; a first conductive feature coupled to the bottom substrate surface, wherein the first conductive feature only partially covers the bottom substrate surface to define a first conductor-less region that spans a first portion of the bottom substrate surface; a first transistor formed at the top substrate surface, wherein the first transistor includes a first control terminal, a first current conducting terminal, and a second current conducting terminal, wherein the first current conducting terminal is electrically coupled to the first conductive feature; and a first filter circuit electrically coupled to the second current conducting terminal, wherein the first filter circuit includes a first inductor formed over a portion of the top substrate surface that is directly opposite the first conductor-less region. 2 . The amplifier of claim 1 , wherein the first inductor is a spiral inductor comprising portions of one or more conductive layers formed over the top substrate surface. 3 . The amplifier of claim 1 , wherein the first filter circuit is selected from a low pass filter circuit, a high pass filter circuit, and a band pass filter circuit. 4 . The amplifier of claim 1 , further comprising: a second conductive feature coupled to the bottom substrate surface and physically separated from the first conductive feature across the first conductor-less region, wherein the second current conducting terminal is electrically coupled to the second conductive feature. 5 . The amplifier of claim 4 , wherein the second current conducting terminal is electrically coupled to the second conductive feature with at least one conductive structure selected from a through substrate via (TSV) and a wrap-around termination. 6 . The amplifier of claim 4 , wherein: the first inductor has first and second inductor terminals, the first inductor terminal is electrically coupled to the second current conducting terminal and to the second conductive feature, the first filter circuit further includes a capacitor with first and second capacitor plates, the first capacitor plate is electrically coupled to the second inductor terminal at a radio frequency (RF) cold point node, and the second capacitor plate is electrically coupled to the first conductive feature. 7 . The amplifier of claim 6 , further comprising: a third conductive feature coupled to the bottom substrate surface and physically separated from the first and second conductive features across the bottom substrate surface, wherein the RF cold point node is electrically coupled to the third conductive feature. 8 . The amplifier of claim 7 , wherein: the RF cold point node is electrically coupled to the third conductive feature through at least one first TSV that extends between the top and bottom substrate surfaces, and the second capacitor plate is electrically coupled to the first conductive feature through at least one second TSV that extends between the top and bottom substrate surfaces. 9 . The amplifier of claim 6 , wherein the first and second capacitor plates comprise portions of first and second conductive layers formed over the top substrate surface. 10 . The amplifier of claim 4 , further comprising: a third conductive feature that is physically separated from the first conductive feature across a second conductor-less region spanning a second portion of the bottom substrate surface; and a second filter circuit electrically coupled to the first control terminal and to the third conductive feature. 11 . The amplifier of claim 10 , wherein the second filter circuit includes a second inductor formed over a portion of the top substrate surface is directly opposite the second conductor-less region. 12 . The amplifier of claim 10 , further comprising: a first conductive lead coupled to the second conductive feature; and a second conductive lead coupled to the third conductive feature. 13 . The amplifier of claim 10 , wherein the second filter circuit is selected from a low pass filter circuit, a high pass filter circuit, and a band pass filter circuit. 14 . The amplifier of claim 4 , wherein: the first current conducting terminal is electrically coupled to the first conductive feature through at least one first TSV that extends between the top and bottom substrate surfaces, and the second current conducting terminal is electrically coupled to the second conductive feature through at least one second TSV that extends between the top and bottom substrate surfaces. 15 . The amplifier of claim 4 , wherein: the first and second conductive features form portions of a patterned conductive layer coupled to the bottom substrate surface, and the patterned conductive layer has a thickness in a range of 10 microns to 50 microns. 16 . The amplifier of claim 4 , further comprising: a second transistor formed in and over the semiconductor substrate, wherein the second transistor includes a second control terminal, a third current conducting terminal, and a fourth current conducting terminal; a third conductive feature coupled to the bottom substrate surface and physically separated from the first and second conductive features across a second conductor-less region spanning a second portion of the bottom substrate surface; and a second filter circuit electrically coupled to the third current conducting terminal, wherein the second filter circuit includes a second inductor formed over a portion of the top substrate surface that is directly opposite the second conductor-less region. 17 . The amplifier of claim 1 , further comprising: a second transistor formed in and over the semiconductor substrate, wherein the second transistor includes a second control terminal, a third current conducting terminal, and a fourth current conducting terminal, and wherein the third current conducting terminal is electrically coupled to the first conductive feature; and a second filter circuit electrically coupled to the fourth current conducting terminal, wherein the second filter circuit includes a second inductor formed over a second portion of the top substrate surface that is directly opposite the first conductor-less region. 18 . The amplifier of claim 1 , wherein the semiconductor substrate is a high resistivity substrate. 19 . The amplifier of claim 1 , further comprising: encapsulant formed over the top substrate surface. 20 . An amplifier comprising: a monolithic active circuit that includes a semiconductor substrate having a top substrate surface and a bottom substrate surface, a first conductive feature coupled to a first region of the bottom substrate surface, wherein the first conductive feature only partially covers the bottom substrate surface, a second conductive feature coupled to a second region of the bottom substrate surface that is separated from the first region by a first conductor-less region spanning a first portion of the bottom substrate surface, a transistor formed at the top substrate surface, wherein the transistor includes a control terminal, a first current conducting terminal, and a second current conducting terminal, wherein the first current conducting terminal is electrically coupled to the first conductive feature, and wherein the second current conducting terminal is electrically coupled to the second conductive feature, and a first filter circuit electrically co
Cutting or separating of wafers, substrates or parts of devices · CPC title
the semiconductor body being completely enclosed · CPC title
using batch processing · CPC title
batch processes · CPC title
for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title
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