Devices and systems for power conversion circuits

US9105560B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105560-B2
Application numberUS-201314105569-A
CountryUS
Kind codeB2
Filing dateDec 13, 2013
Priority dateDec 21, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

First claim

Opening claim text (preview).

The invention claimed is: 1. A system comprising a cascode arrangement of a normally-on depletion mode high voltage GaN FET driven by a normally-off driver MOSFET, and a driver circuit; wherein the GaN FET is fabricated on a first substrate die (GaN die) and the driver circuit comprises a CMOS driver circuit fabricated on a second substrate die (CMOS die), the driver MOSFET being integrated with the driver circuit; the GaN die comprising an arrangement of a plurality of front-si…

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What does patent US9105560B2 cover?
Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN…
Who is the assignee on this patent?
Gan Systems Inc
What technology area does this patent fall under?
Primary CPC classification H01L25/18. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).