Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

Patent metadata

Field	Value
Publication number	US-11335673-B2
Application number	US-201816191720-A
Country	US
Kind code	B2
Filing date	Nov 15, 2018
Priority date	Dec 22, 2017
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first active region and a second active region, each extending on a substrate in a first horizontal direction, wherein the first active region and the second active region extend in parallel and have conductivity types different from each other;
a first gate line extending in a second horizontal direction that crosses the first horizontal direction, wherein the first gate line forms, with the first active region, a first transistor, and wherein the first transistor comprises a gate configured to receive a first input signal;
a second gate line extending in the second horizontal direction, wherein the second gate line forms, with the second active region, a second transistor, and wherein the second transistor comprises a gate configured to receive the first input signal; and
a third gate line continually extending in the second horizontal direction from the first active region to the second active region, between the first and second gate lines, and forming, with the first and second active regions, a third transistor and a fourth transistor, respectively, wherein each of the third and fourth transistors comprises a gate configured to receive a second input signal,
wherein the first gate line comprises a first partial gate line that overlaps the first active region in a third direction perpendicular to the first horizontal direction and the second horizontal direction, and wherein the first partial gate line comprises an end on a region between the first and second active regions,
wherein the second gate line comprises a second partial gate line overlapping the second active region in the third direction and having an end on a region between the first and second active regions, the second gate line further comprising a second dummy gate line having at least a portion that overlaps the first active region in the third direction and that is spaced apart from the second partial gate line,
wherein a portion of the first active region that is between the second partial gate line and the second dummy gate line is free of overlap, in the third direction, from the second gate line, and
wherein the integrated circuit further comprises a second jumper electrically interconnecting source/drain regions arranged on the first active regions at both sides of the second dummy gate line.

2. The integrated circuit of claim 1 , wherein the first gate line further comprises a first dummy gate line that comprises at least a portion which overlaps the second active region in the third direction and is spaced apart from the first partial gate line,
the integrated circuit further comprising:
a first jumper electrically interconnecting source/drain regions arranged on the second active region at both sides of the first dummy gate line.

3. The integrated circuit of claim 2 , wherein the first jumper comprises:
source/drain contacts having bottom surfaces connected to the source/drain regions, respectively.

4. The integrated circuit of claim 3 , wherein the first jumper comprises:
an upper contact extending in the first horizontal direction and having a bottom surface connected to the source/drain contacts.

5. The integrated circuit of claim 1 , further comprising:
an interconnection electrically connecting the gates of the first and second transistors,
wherein the interconnection comprises a first metal pattern that includes a first portion and a second portion extending in the second horizontal direction on the first and second gate lines, respectively, and a third portion connected to ends of the first and second portions and extending in the first horizontal direction.

6. The integrated circuit of claim 5 , further comprising:
a second metal pattern electrically connected to the third gate line and extending in the second horizontal direction between the first and second portions of the first metal pattern.

7. The integrated circuit of claim 6 , wherein the second metal pattern has a length in the second horizontal direction, which is less than a length based on a design rule.

8. An integrated circuit comprising:
a first active region and a second active region, each extending on a substrate in a first horizontal direction, wherein the first active region and the second active region extend in parallel and have conductivity types different from each other;
a first gate line extending in a second horizontal direction that crosses the first horizontal direction, wherein the first gate line comprises a first partial gate line that forms, with the first active region, a first transistor having a gate configured to receive a first input signal, and wherein the first gate line further comprises a first dummy portion which overlaps the second active region in a third direction and is insulated from the first partial gate line;
a second gate line extending in the second horizontal direction, wherein the second gate line comprises a second partial gate line that forms, with the second active region, a second transistor having a gate configured to receive the first input signal, and wherein the second gate line further comprises a second dummy portion which overlaps the first active region in the third direction and is insulated from the second partial gate line; and
a third gate line continually extending in the second horizontal direction from the first active region to the second active region, between the first and second gate lines, and forming, with the first and second active regions, a third transistor and a fourth transistor, respectively, wherein each of the third and fourth transistors comprises a gate configured to receive a second input signal,
wherein a portion of the first active region between the second partial gate line and the second dummy portion is free of overlap, in the third direction, from the second gate line.

9. The integrated circuit of claim 8 , further comprising:
a first jumper electrically interconnecting source/drain regions arranged on the second active region at both sides of the first dummy portion of the first gate line.

10. An integrated circuit comprising:
a first active region and a second active region, each extending on a substrate in a first horizontal direction, wherein the first active region and the second active region extend in parallel and have conductivity types different from each other;
a first gate line extending in a second horizontal direction that crosses the first horizontal direction, wherein the first gate line comprises a first partial gate line that forms, with the first active region, a first transistor having a gate configured to receive a first input signal, and wherein the first gate line further comprises a first dummy portion which overlaps the second active region in a third direction and is separated from the first partial gate line by a first cutting region;
a second gate line extending in the second horizontal direction, wherein the second gate line comprises a second partial gate line that forms, with the second active region, a second transistor having a gate configured to receive the first input signal, wherein the second gate line further comprises a second dummy portion which overlaps the first active region in the third direction and is separated from the second partial gate line by a second cutting region, and wherein a portion of the first active region between the second partial gate line and the second dummy portion is free of overlap, in the third direction, from the second gate line; and
a third gate line continually extending in the second horizontal direction from the first active region to the second active region, between the first and second gate lines, and forming, with the first and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Lee Dal-Hee
• Lim Jin-Young
• Song Tae-Joong
• Jung Jong-Hoon

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/432

  comprising crossing interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title