Wafer test structures and methods of providing wafer test structures
US-2016025805-A1 · Jan 28, 2016 · US
Semiconductor devices and methods for manufacturing the same
US9704862B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9704862-B2 |
| Application number | US-201514854358-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2015 |
| Priority date | Sep 18, 2014 |
| Publication date | Jul 11, 2017 |
| Grant date | Jul 11, 2017 |
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- Title
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Abstract
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According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a substrate including a PMOSFET region and an NMOSFET region; a first gate electrode and a second gate electrode on the PMOSFET region; a third gate electrode and a fourth gate electrode on the NMOSFET region, the first to fourth gate electrodes defining a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes; and a first contact and a second contac…
Assignees
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Classifications
- H10D84/85Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9704862B2 cover?
- According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact c…
- Who is the assignee on this patent?
- Park Panjae, Kim Sutae, Kim Donghyun, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/85. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).