Method for fabricating a semiconductor device comprising a paste layer and semiconductor device

US11329021B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11329021-B2
Application numberUS-201916685318-A
CountryUS
Kind codeB2
Filing dateNov 15, 2019
Priority dateNov 15, 2018
Publication dateMay 10, 2022
Grant dateMay 10, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating a semiconductor device comprising a paste layer, the method comprising: attaching a substrate to a first carrier, the substrate comprising a plurality of semiconductor dies; applying a layer of a paste to the substrate; precuring the paste, wherein precuring the paste comprises applying electromagnetic irradiation; structuring the layer above cutting regions of the substrate; attaching the layer to a second carrier; removing the first carrier from the substrate; and cutting the substrate along the cutting regions. 2. The method of claim 1 , wherein the paste comprises an electrically conductive material. 3. The method of claim 2 , wherein the paste is a sinter paste. 4. The method of claim 1 , where the electromagnetic radiation comprises microwaves or photonic curing. 5. The method of claim 1 , where applying electromagnetic radiation includes using a laser or high energy flash lamp. 6. The method of claim 1 , wherein precuring the paste comprises in addition applying heat in a range of 25° C. to 250° C. 7. The method of claim 1 , wherein the semiconductor dies comprise a backside metallization layer and wherein the paste is applied to the backside metallization layer. 8. The method of claim 1 , wherein the substrate comprises a reinforcing structure and wherein the method further comprises: removing the reinforcing structure prior to applying the paste. 9. The method of claim 4 , wherein the structuring comprises removing the paste above the cutting regions after the precuring. 10. The method of claim 9 , wherein the paste is removed by physical or chemical methods. 11. The method of claim 1 , further comprising: masking the substrate above the cutting regions prior to applying the paste. 12. The method of claim 11 , wherein the substrate is masked using photoresist. 13. The method of claim 1 , wherein the structuring comprises arranging a photomask on the layer of the paste and removing the paste above the cutting regions. 14. The method of claim 1 , wherein the second carrier is a temporary carrier and wherein the method further comprises: removing the plurality of semiconductor dies from the temporary carrier. 15. The method of claim 1 , wherein the applying the layer of the paste comprises a printing process. 16. The method of claim 1 , wherein the applying the layer of the paste comprises transferring the paste from a film onto the substrate.

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What does patent US11329021B2 cover?
A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cu…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W72/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 10 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).