Method for processing a semiconductor substrate and a method for processing a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-9673096-B2
Application number	US-201414541239-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

First claim

What is claimed is:

1. A method comprising:
covering a plurality of die regions of a semiconductor substrate with a metal to be annealed;
forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal, and, subsequently,
annealing the metal covering at least one die of the plurality of dies,
wherein covering the plurality of die regions with a metal comprises printing a suspension containing the metal over the plurality of die regions of the semiconductor substrate.

2. The method of claim 1 , further comprising:
pre-annealing the suspension after printing.

3. The method of claim 1 ,
wherein printing the suspension comprises stencil printing.

4. The method of claim 1 ,
wherein the metal comprises copper.

5. The method of claim 1 ,
wherein the semiconductor substrate is a semiconductor wafer.

6. The method of claim 1 ,
wherein the semiconductor substrate has a thickness less than 100 μm.

7. The method of claim 1 ,
wherein the metal covering each die of the plurality of dies has a thickness greater than or equal to 25% of a thickness of the semiconductor substrate.

8. The method of claim 1 ,
wherein forming the plurality of dies from the semiconductor substrate comprises dicing.

9. The method of claim 1 ,
wherein forming the plurality of dies from the semiconductor substrate comprises plasma dicing and wherein the metal covering the plurality of die regions of the semiconductor substrate is used as mask for the plasma dicing.

10. The method of claim 9 , further comprising:
mounting the semiconductor substrate on a glass carrier before dicing so that the dies of the plurality of dies are adhered to the glass carrier after dicing.

11. The method of claim 1 , further comprising:
adhering the at least one die of the plurality of dies with the metal to a metal layer before the annealing.

12. The method of claim 1 , further comprising:
adhering the at least one die of the plurality of dies to an auxiliary carrier before the annealing.

13. The method of claim 1 ,
wherein the metal covering the plurality of die regions of the semiconductor substrate forms a backside metallization.

14. A method comprising:
printing a layer over a semiconductor wafer, the layer comprising metal particles;
pre-annealing the layer;
separating the semiconductor wafer into a plurality of dies, wherein each die of the plurality of dies is covered with metal particles of the pre-annealed layer; and, subsequently,
sintering the metal particles of the pre-annealed layer.

15. The method of claim 14 ,
wherein separating the semiconductor wafer comprises plasma dicing.

16. The method of claim 14 ,
wherein the sintered metal particles provide a backside metallization.

17. The method of claim 14 ,
wherein the metal particles comprise copper particles.

Assignees

• Infineon Technologies Ag
• Univ Graz Tech

Inventors

• Hirschler Joachim
• Roesner Michael
• Heinrici Markus Juch
• Stranzl Gudrun
• Mischitz Martin
• Zgaga Martin

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/925

  Bond pads having a filler embedded in a matrix · CPC title