Semiconductor package electrical contacts and related methods

Patent metadata

Field	Value
Publication number	US-2020258752-A1
Application number	US-202016861910-A
Country	US
Kind code	A1
Filing date	Apr 29, 2020
Priority date	Aug 17, 2017
Publication date	Aug 13, 2020
Grant date	—

Abstract

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a semiconductor die comprising a first side and a second side, the first side of the semiconductor die comprising one or more electrical contacts; an organic material covering at least the first side of the semiconductor die wherein the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

2 . The package of claim 1 , wherein the one or more slugs are coupled directly to the metal-containing layer.

3 . The package of claim 1 , wherein the one or more electrical contacts comprise a bump coupled to a die pad coupled to the first side of the semiconductor die.

4 . The package of claim 1 , wherein the organic material is a mold compound.

5 . The package of claim 1 , wherein the metal-containing layer is a solder resist layer.

6 . The package of claim 1 , wherein the semiconductor die comprises a thickness between 0.1 microns and 125 microns.

7 . The package of claim 1 , wherein the one or more electrical contacts are one of bumps or studs, the second side of the die further comprises a backmetal, and the one or more slugs are coupled to the backmetal.

8 . A method of forming a semiconductor package, comprising:
providing a semiconductor substrate comprising a plurality of semiconductor die, the semiconductor substrate comprising a first side and a second side; forming one or more electrical contacts on the first side of the semiconductor die, the one or more electrical contacts coupled with the plurality of semiconductor die; applying an organic material to the first side of the semiconductor die wherein the one or more electrical contacts extend into one or more openings in the organic compound; leveling the organic material with a surface of the one or more electrical contacts; and directly coupling one or more slugs to one or more of the one or more electrical contacts or to the second side of the semiconductor substrate.

9 . The method of claim 8 , wherein the one or more slugs are coupled directly to a metal-containing layer comprised in the one or more electrical contacts.

10 . The method of claim 9 , wherein the metal-containing layer is a solder resist material.

11 . The method of claim 8 , wherein the one or more electrical contacts are coupled to a pad comprised in the plurality of semiconductor die.

12 . The method of claim 8 , further comprising grooving a surface of the semiconductor substrate at a plurality of die streets between the plurality of semiconductor die.

13 . The method of claim 8 , further comprising forming a backmetal on the second side of the semiconductor substrate.

14 . The method of claim 13 , further comprising directly coupling the one or more slugs to the backmetal.

15 . The method of claim 8 , further comprising thinning the semiconductor substrate to a thickness of 0.1 microns to 125 microns.

16 . The method of claim 8 , wherein the plurality of electrical contacts are one of bumps or studs that extend above the organic material and the one or more slugs are directly coupled with the second side of the semiconductor substrate.

17 . A method of forming a semiconductor package, comprising:
providing a semiconductor substrate comprising a plurality of semiconductor die, the semiconductor substrate comprising a first side and a second side; forming one or more electrical contacts on the first side of the semiconductor die by forming at least a portion of the one or more electrical contacts to a predetermined height, the one or more electrical contacts coupled with the plurality of semiconductor die; applying an organic material to the first side of the semiconductor die wherein the one or more electrical contacts extend into one or more openings in the organic compound; and leveling the organic material with a surface of the one or more electrical contacts; wherein the predetermined height of the formed portion of the one or more electrical contacts reduces warpage of the semiconductor package to below 200 microns.

18 . The method of claim 17 , wherein forming the one or more electrical contacts comprises electroplating.

19 . The method of claim 17 , wherein forming the plurality of electrical contacts comprises evaporating, sputtering, soldering, screen printing, silver sintering and any combination thereof.

20 . The method of claim 17 , wherein the organic material is a mold compound.

Assignees

• Semiconductor Components Ind

Inventors

• Lin Yusheng
• Seddon Michael J
• Carney Francis J
• Noma Takashi
• Kurose Eiji

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title