Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips

Patent metadata

Field	Value
Publication number	US-9786627-B2
Application number	US-201214348356-A
Country	US
Kind code	B2
Filing date	Sep 10, 2012
Priority date	Oct 15, 2011
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body.

First claim

What is claimed is:

1. A method for creating a connection of a power semiconductor chip having upper side potential faces with thick wires or strips, comprising:
providing a carrying sheet with a plurality of metallic moulded bodies corresponding to the shape of the upper side potential faces, wherein the carrying sheet has a plurality of windows provided above central partial faces of the plurality of metallic moulded bodies,
applying a bonding layer on the upper side potential faces or the plurality of metallic moulded bodies,
placing the plurality of metallic moulded bodies and creating a cohesive, electrically conducting connection to the upper side potential faces, and
removing the carrying sheet after bonding the plurality of metallic moulded bodies to the upper side potential faces.

2. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein the moulded bodies provided comprise at least one metal of the group of Cu, Ag, Au, Mo, Al, W or their alloys, the alloys comprising one or more of the metals of the group mentioned.

3. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein by means of the bonding layer, moulded bodies and potential faces are bonded by means of sintering, diffusion soldering or gluing to the power semiconductor chip.

4. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein the carrying sheet is an organic carrying sheet.

5. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

6. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

7. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein the carrying sheet with a number of moulded bodies corresponding to the number of potential faces is applied on two or more unseparated power semiconductor chips before bonding.

8. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein the carrying sheet is removed while the power semiconductor chip is unseparated.

9. The method for creating a connection of a power semiconductor chip according to claim 1 , wherein above the central partial faces of the moulded bodies meant for bonding, the carrying sheet is not provided with adhesive.

10. The method for creating a connection of a power semiconductor chip according to claim 2 , wherein by means of the bonding layer, moulded bodies and potential faces are bonded by means of sintering, diffusion soldering or gluing to the power semiconductor chip.

11. The method for creating a connection of a power semiconductor chip according to claim 2 , wherein the carrying sheet is an organic carrying sheet.

12. The method for creating a connection of a power semiconductor chip according to claim 3 , wherein the carrying sheet is an organic carrying sheet.

13. The method for creating a connection of a power semiconductor chip according to claim 2 , wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

14. The method for creating a connection of a power semiconductor chip according to claim 3 , wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

15. The method for creating a connection of a power semiconductor chip according to claim 4 , wherein an additional moulded body having the shape of a bottom side of the power semiconductor chip is provided to be cohesively connected with a bonding layer on the bottom side of the power semiconductor chip lying opposite to the upper side potential faces.

16. The method for creating a connection of a power semiconductor chip according to claim 2 , wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

17. The method for creating a connection of a power semiconductor chip according to claim 3 , wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

18. The method for creating a connection of a power semiconductor chip according to claim 4 , wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

19. The method for creating a connection of a power semiconductor chip according to claim 5 , wherein an electrically insulating material that can resist the thermal load of the bonding is used for the carrying sheet.

20. The method for creating a connection of a power semiconductor chip according to claim 2 , wherein the carrying sheet with a number of moulded bodies corresponding to the number of potential faces is applied on two or more unseparated power semiconductor chips before bonding.

21. A method for creating a connection of a power semiconductor chip having upper side potential faces with thick wires or strips, comprising:
providing a carrying sheet with a plurality of metallic moulded bodies corresponding to the shape of the upper side potential faces, wherein the carrying sheet does not have adhesive above central partial faces of the plurality of metallic moulded bodies meant for bonding,
applying a bonding layer on the upper side potential faces or the plurality of metallic moulded bodies,
placing the metallic moulded bodies and creating a cohesive, electrically conducting connection to the potential faces, wherein there is no thick-wire bonded on non-bonded upper sides of the plurality of metallic moulded bodies; and
removing the carrying sheet after bonding the plurality of metallic moulded bodies to the upper side potential faces.

22. The method for creating a connection of a power semiconductor chip according to claim 1 , further comprising the step of: thick-wire bonding on non-bonded upper sides of the plurality of metallic moulded bodies.

Assignees

• Becker Martin
• Eisele Ronald
• Osterwald Frank
• Rudzki Jacek
• Danfoss Silicon Power Gmbh

Inventors

• Becker Martin
• Eisele Ronald
• Osterwald Frank
• Rudzki Jacek

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title