Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same

Patent metadata

Field	Value
Publication number	US-11316024-B2
Application number	US-202117165934-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Sep 30, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions;
a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region;
a first coupling gate disposed over and insulated from the first floating gate;
a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region;
a first erase gate disposed over and insulated from the first word line gate;
a third region in the substrate having the second conductivity type, with a second channel region in the substrate extending between the first and third regions;
a second floating gate disposed over and insulated from a first portion of the second channel region adjacent to the third region;
a second coupling gate disposed over and insulated from the second floating gate;
a second word line gate disposed over and insulated from a second portion of the second channel region adjacent the first region; and
a second erase gate disposed over and insulated from the second word line gate;
wherein the first erase gate includes a notch facing an edge of the first floating gate, and the second erase gate includes a notch facing an edge of the second floating gate.

2. The memory device of claim 1 , wherein the first floating gate is partially disposed over and insulated from the second region, and the second floating gate is partially disposed over and insulated from the third region.

3. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions;
a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region;
a first coupling gate disposed over and insulated from the first floating gate;
a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region;
a first erase gate disposed over and insulated from the first word line gate;
a third region in the substrate having the second conductivity type, with a second channel region in the substrate extending between the first and third regions;
a second floating gate disposed over and insulated from a first portion of the second channel region adjacent to the third region;
a second coupling gate disposed over and insulated from the second floating gate;
a second word line gate disposed over and insulated from a second portion of the second channel region adjacent the first region; and
a second erase gate disposed over and insulated from the second word line gate;
wherein insulation between the first word line gate and the substrate is thinner than insulation between the first floating gate and the substrate, and wherein insulation between the second word line gate and the substrate is thinner than insulation between the second floating gate and the substrate.

4. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions;
a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region;
a first coupling gate disposed over and insulated from the first floating gate;
a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region;
a first erase gate disposed over and insulated from the first word line gate;
a third region in the substrate having the second conductivity type, with a second channel region in the substrate extending between the first and third regions;
a second floating gate disposed over and insulated from a first portion of the second channel region adjacent to the third region;
a second coupling gate disposed over and insulated from the second floating gate;
a second word line gate disposed over and insulated from a second portion of the second channel region adjacent the first region; and
a second erase gate disposed over and insulated from the second word line gate;
wherein insulation between the first erase gate and the first floating gate is thinner than insulation between the first word line gate and the first floating gate, and wherein insulation between the second erase gate and the second floating gate is thinner than insulation between the second word line gate and the second floating gate.

5. The memory device of claim 1 , wherein:
the first word line gate is disposed laterally adjacent to and insulated from the first floating gate;
the first erase gate is disposed laterally adjacent to and insulated from the first coupling gate;
the second word line gate is disposed laterally adjacent to and insulated from the second floating gate; and
the second erase gate is disposed laterally adjacent to and insulated from the second coupling gate.

6. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions;
a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region;
a first coupling gate disposed over and insulated from the first floating gate;
a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region;
a first erase gate disposed over and insulated from the first word line gate; and
control circuitry configured to:
program the first floating gate by applying positive voltages to the first erase gate, the first word line gate, the first coupling gate and the second region, and a current to the first region;
read the first floating gate by applying positive voltages to the first word line gate, the first coupling gate and the first region; and
erase the first floating gate by applying a positive voltage to the first erase gate.

7. The memory device of claim 3 , wherein:
the first word line gate is disposed laterally adjacent to and insulated from the first floating gate;
the first erase gate is disposed laterally adjacent to and insulated from the first coupling gate;
the second word line gate is disposed laterally adjacent to and insulated from the second floating gate; and
the second erase gate is disposed laterally adjacent to and insulated from the second coupling gate.

8. The memory device of claim 4 , wherein:
the first word line gate is disposed laterally adjacent to and insulated from the first floating gate;
the first erase gate is disposed laterally adjacent to and insulated from the first coupling gate;
the second word line gate is disposed laterally adjacent to and insulated from the second floating gate; and
the second erase gate is disposed laterally adjacent to and insulated from the second coupling gate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Liu Xian
• Song guo xiang
• Xing leo
• Do Nhan

Classifications

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C2216/04

  Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate · CPC title