Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling

Patent metadata

Field	Value
Publication number	US-10312246-B2
Application number	US-201514790540-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Aug 8, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

First claim

What is claimed is:

1. A non-volatile memory cell, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second spaced-apart regions in the substrate of a second conductivity type different from the first conductivity type, with a channel region in the substrate therebetween;
an electrically conductive floating gate having a first portion disposed vertically over and insulated from a first portion of the channel region, and a second portion disposed vertically over and insulated from the first region, wherein the floating gate includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate;
an electrically conductive erase gate disposed vertically over and insulated from the floating gate, wherein the pair of sharp edges face and are insulated from the erase gate, wherein the erase gate has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the floating gate, and wherein the bottom surface of the erase gate further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges;
an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gate, and vertically over and insulated from the first region; and an electrically conductive select gate having a first portion disposed vertically over and insulated from a second portion of the channel region, and laterally adjacent to and insulated from the floating gate.

2. The non-volatile memory cell of claim 1 , wherein the control gate has a second portion disposed laterally adjacent to and insulated from the erase gate.

3. The non-volatile memory cell of claim 1 , wherein the select gate has a second portion disposed laterally adjacent to and insulated from the erase gate.

4. The non-volatile memory cell of claim 1 , wherein the select gate is a spacer.

5. The non-volatile memory cell of claim 1 , wherein the floating gate includes:
a bottom surface facing the first portion of the channel region and the first region; and
a side surface facing the control gate;
wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

6. An array of non-volatile memory cells, comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including pairs of memory cells, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate having a second conductivity type different from the first conductivity type, with channel regions in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each having a first portion disposed vertically over and insulated from a first portion of a respective one of the channel regions, and a second portion disposed vertically over and insulated from the first region, wherein each floating gate of the pair of floating gates includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate,
a pair of electrically conductive erase gates, each erase gate of the pair of erase gates disposed vertically over and insulated from a respective floating gate of the pair of floating gates, wherein the pair of sharp edges of each floating gate of the pair of floating gates face a respective erase gate of the pair of erase gates, wherein each erase gate of the pair of erase gates has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the respective floating gate, and wherein the bottom surface of each erase gate of the pair of erase gates further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges of the respective floating gate,
an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the pair of floating gates, and vertically over and insulated from the first region, and
a pair of electrically conductive select gates each having a first portion disposed vertically over and insulated from a second portion of a respective one of the channel regions, and laterally adjacent to and insulated from a respective floating gate of the pair of floating gates;
wherein each of the erase gates is formed as part of a conductive erase gate line that extends across the active regions and the isolation regions in a second direction perpendicular to the first direction, and wherein each of the erase gate lines intercepts one of the erase gates in each of the active regions.

7. The array of claim 6 , wherein for each of the memory cell pairs, the control gate has a second portion disposed laterally between and insulated from the pair of erase gates.

8. The array of claim 6 , wherein for each of the memory cell pairs each select gate of the pair of select gates has a second portion disposed laterally adjacent to and insulated from a respective erase gate of the pair of erase gates.

9. The array of claim 6 , wherein each of the select gates is a spacer.

10. The array of claim 6 , wherein for each of the memory cell pairs, each floating gate of the pair of floating gates includes:
a bottom surface facing the first portion of the respective one of the channel regions and the first region; and
a side surface facing the control gate;
wherein the side surface has a vertical length that is greater than a horizontal length of the bottom surface.

11. A method of forming a nonvolatile memory cell, comprising:
providing a substrate of semiconductor material of a first conductivity type;
forming first and second spaced-apart regions in the substrate of a second conductivity type different from the first conductivity type, with a channel region in the substrate therebetween;
forming an electrically conductive floating gate having a first portion disposed vertically over and insulated from a first portion of the channel region, and a second portion disposed vertically over and insulated from the first region, wherein the floating gate includes a sloping upper surface that terminates with a pair of sharp edges at opposing sides of the sloping upper surface of the floating gate;
forming an electrically conductive erase gate disposed vertically over and insulated from the floating gate, wherein the pair of sharp edges face and are insulated from the erase gate, wherein the erase gate has a bottom surface with a portion facing, and having a shape matching that of, the sloping upper surface of the floating gate, and wherein the bottom surface of the erase gate further includes a pair of portions, each portion of the pair of portions wraps around a respective sharp edge of the pair of sharp edges;
forming an electrically conductive control gate having a first portion disposed laterally adjacent to and insulated from the floating gate, and vertically over and insulated from the first region; and
forming an electrically conductive select gate having a first portion disposed vertically over and insulated from a second portion of the channel region, and laterally adjacent to and insulated from the floating gate.

12. The method of claim 11 , wherein the forming of the select gate includes form

Assignees

• Silicon Storage Tech Inc

Inventors

• Yang Jeng-Wei
• Wu Man-Tang
• Chen Chun-Ming
• Su Chien-Sheng
• Do Nhan

Classifications

• H01L21/823475

  Electricity · mapped topic

• H01L21/823425

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic