Virtual ground non-volatile memory array

Patent metadata

Field	Value
Publication number	US-10312248-B2
Application number	US-201514935201-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Nov 12, 2014
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions,
a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region,
a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region,
an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions,
a first control gate disposed vertically over and insulated from the first floating gate, and
a second control gate disposed vertically over and insulated from the second floating gate;

wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;
a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;
a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;
a plurality of bit lines having lengths extending in the second direction and each electrically connected to one of the first regions and one of the second regions in each of the active regions; and
a plurality of erase gate lines having lengths extending in the first direction and each electrically connected to the erase gates in one of the active regions;
wherein the erase gate lines are metal lines having lengths extending in the first direction and are disposed vertically over the active regions and electrically connected to the erase gates via vertically extending contacts.

2. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;
each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions,
a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region,
a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region,
an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions,
a first control gate disposed vertically over and insulated from the first floating gate, and
a second control gate disposed vertically over and insulated from the second floating gate;

wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;
a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;
a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;
a plurality of bit lines having lengths extending in the second direction and each electrically connected to one of the first regions and one of the second regions in each of the active regions; and
a plurality of erase gate lines having lengths extending in the first direction and each electrically connected to the erase gates in one of the active regions;
wherein each of the erase gates extends into one of the isolation regions, and wherein the erase gate lines are metal lines having lengths extending in the first direction and are disposed vertically over the isolations regions and electrically connected to the erase gates via vertically extending contacts in the isolation regions.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Nguyen Hung Quoc
• Do Nhan

Classifications

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H01L29/42328

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic