Split-gate, twin-bit non-volatile memory cell

Patent metadata

Field	Value
Publication number	US-9972632-B2
Application number	US-201715476663-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Apr 29, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate of semiconductor material of a first conductivity type;
first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions;
a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region;
a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region;
a word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions;
a first erase gate disposed over and insulated from the first region; and
a second erase gate disposed over and insulated from the second region.

2. The memory device of claim 1 , wherein the first floating gate is partially disposed over and insulated from the first region, and the second floating gate is partially disposed over and insulated from the second region.

3. The memory device of claim 1 , wherein the first erase gate includes a notch facing an edge of the first floating gate, and wherein the second erase gate includes a notch facing an edge of the second floating gate.

4. The memory device of claim 1 , wherein:
the word line gate is insulated from the first floating by first insulation, the first floating gate is insulated from the first erase gate by second insulation, and the first insulation is thicker than the second insulation; and
the word line gate is insulated from the second floating by third insulation, the second floating gate is insulated from the second erase gate by fourth insulation, and the third insulation is thicker than the fourth insulation.

5. The memory device of claim 1 , wherein:
the first floating gate includes a first upper surface that slopes downwardly as the first upper surface extends away from the first erase gate; and
the second floating gate includes a second upper surface that slopes downwardly as the second upper surface extends away from the second erase gate.

6. The memory device of claim 1 , further comprising:
a first coupling gate disposed over and insulated from the first floating gate; and
a second coupling gate disposed over and insulated from the second floating gate.

7. The memory device of claim 6 , further comprising:
control circuitry configured to:
program the first floating gate by applying a positive voltage to the first erase gate, a zero voltage to the second erase gate, a positive voltage to the word line gate, a positive voltage to the first coupling gate, a positive voltage to the second coupling gate, a positive voltage to the first region and a current to the second region;
read the first floating gate by applying a zero voltage to the first and second erase gates, the first coupling gate and the first region, a positive voltage to the word line gate, a positive voltage to the second coupling gate, and a positive voltage to the second region; and
erase the first floating gate by applying a positive voltage to the first erase gate and a negative voltage to the first coupling gate.

8. The memory device of claim 1 , further comprising:
control circuitry configured to:
program the first floating gate by applying a positive voltage to the first erase gate, a zero voltage to the second erase gate, a positive voltage to the word line gate, a positive voltage to the first region and a current to the second region;
read the first floating gate by applying a zero voltage to the first erase gate and the first region, a positive voltage to the second erase gate, a positive voltage to the word line gate and a positive voltage to the second region; and
erase the first floating gate by applying a positive voltage to the first erase gate.

9. A method of operating a memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type with a continuous channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, a word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, a first erase gate disposed over and insulated from the first region, a second erase gate disposed over and insulated from the second region, a first coupling gate disposed over and insulated from the first floating gate, and a second coupling gate disposed over and insulated from the second floating gate, the method comprising:
programming the first floating gate by applying a positive voltage to the first erase gate, a zero voltage to the second erase gate, a positive voltage to the word line gate, a positive voltage to the first coupling gate, a positive voltage to the second coupling gate, a positive voltage to the first region and a current to the second region;
reading the first floating gate by applying a zero voltage to the first and second erase gates, the first coupling gate and the first region, a positive voltage to the word line gate, a positive voltage to the second coupling gate, and a positive voltage to the second region; and
erasing the first floating gate by applying a positive voltage to the first erase gate and a negative voltage to the first coupling gate.

10. A method of operating a memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type with a continuous channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, a word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, a first erase gate disposed over and insulated from the first region, and a second erase gate disposed over and insulated from the second region, the method comprising:
programming the first floating gate by applying a positive voltage to the first erase gate, a zero voltage to the second erase gate, a positive voltage to the word line gate, a positive voltage to the first region and a current to the second region;
reading the first floating gate by applying a zero voltage to the first erase gate and the first region, a positive voltage to the second erase gate, a positive voltage to the word line gate and a positive voltage to the second region; and

erasing the first floating gate by applying a positive voltage to the first erase gate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Wang Chunming
• Do Nhan

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0433 Primary

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• H01L29/42328

  Electricity · mapped topic