Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

Patent metadata

Field	Value
Publication number	US-10217850-B2
Application number	US-201715474879-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Apr 20, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

First claim

What is claimed is:

1. A method of forming a pair of non-volatile memory cells comprising:
forming a first insulation layer on a semiconductor substrate;
forming a first polysilicon layer on the first insulation layer in a first polysilicon deposition process;
forming a pair of spaced apart insulation blocks directly on the first polysilicon layer, each of the insulation blocks having first sides facing toward each other and second sides facing away from each other;
removing portions of the first polysilicon layer while maintaining portions of the first polysilicon layer disposed underneath the pair of insulation blocks and between the pair of insulation blocks;
forming a pair of spaced apart insulation spacers adjacent the first sides and over a portion of the first polysilicon layer disposed between the pair of insulation blocks, wherein the forming of the insulation spacers includes removing portions of the first insulation layer adjacent the second sides;
removing a portion of the first polysilicon layer disposed between the insulation spacers while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks and one of the pair of insulation spacers;
forming a source region in the substrate and between the pair of insulation blocks;
removing the pair of insulation spacers;
forming insulation material that at least extends along an end portion of each of the pair of polysilicon blocks and along portions of the semiconductor substrate adjacent the second sides;
forming a second polysilicon layer over the substrate and the pair of insulation blocks in a second polysilicon deposition process;
removing portions of the second polysilicon layer while maintaining a first polysilicon block, a second polysilicon block and a third polysilicon block of the second polysilicon layer, wherein:
the first polysilicon block is disposed between the pair of insulation blocks and over the source region,
the second polysilicon block is disposed adjacent the second side of one of the insulation blocks, and
the third polysilicon block is disposed adjacent the second side of another one of the insulation blocks,
wherein the removing of the portions of the second polysilicon layer includes performing a CMP using the pair of insulation blocks as an etch stop to planarize top surfaces of the first, second and third polysilicon blocks;

forming a first drain region in the substrate and adjacent the second polysilicon block; and
forming a second drain region in the substrate and adjacent the third polysilicon block.

2. The method of claim 1 , further comprising:
forming salicide on upper surfaces of the first, second and third polysilicon blocks.

3. The method of claim 1 , wherein the first polysilicon block includes a first portion laterally adjacent to the pair of polysilicon blocks of the first polysilicon layer, and a second portion that extends up and over the pair of polysilicon blocks of the first polysilicon layer.

4. The method of claim 1 , further comprising:
forming a pair of second insulation spacers adjacent the second sides in a same deposition and etch process used to form the pair of spaced apart insulation spacers.

5. The method of claim 1 , wherein the spaced apart insulation blocks are formed of oxide, or a composite of layers including both oxide and nitride.

6. The method of claim 1 , wherein the first insulation layer is formed of oxide or nitrogen treated oxide.

Assignees

• Silicon Storage Tech Inc

Inventors

• Zhou Feng
• Liu Xian
• Su Chien-Sheng
• Do Nhan
• Wang Chunming

Classifications

• G11C2216/10

  Floating gate memory cells with a single polysilicon layer · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L27/0705

  Electricity · mapped topic