Non-volatile split gate memory cells with integrated high K metal gate, and method of making same

Patent metadata

Field	Value
Publication number	US-9634019-B1
Application number	US-201615225393-A
Country	US
Kind code	B1
Filing date	Aug 1, 2016
Priority date	Oct 1, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

First claim

What is claimed is:

1. A method of forming a pair of memory cells, comprising:
forming a polysilicon layer over and insulated from a semiconductor substrate;
forming a pair of spaced apart conductive control gates over and insulated from the polysilicon layer, wherein the control gates having inner side surfaces facing each other and outer side surfaces facing away from each other;
forming a first insulation layer that extends directly along the inner and outer side surfaces of the control gates;
forming a second insulation layer that extends directly along the first insulation layer;
removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates;
forming first insulation spacers that extend directly along the second insulation layer and indirectly along the outer side surfaces of the control gates;
forming second insulation spacers that extend directly along the second insulation and indirectly along the inner side surfaces of the control gates;
forming an HKMG layer extending along the first and second insulation spacers and along portions of the substrate adjacent the outer side surfaces of the control gates, wherein the HKMG layer includes:
a layer of high K insulation material, and
a layer of metal material on the layer of high K insulation material;

removing portions of the HKMG layer extending along the second insulation spacers;
removing the second insulation spacers;
removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates;
forming a source region in the substrate adjacent the inner side surfaces of the control gates;
forming a conductive erase gate over and insulated from the source region, wherein the erase gate is insulated from each of the control gates by at least the first insulation layer and the second insulation layer;
forming conductive word line gates laterally adjacent to the first insulation spacers, wherein for each of the word line gates, the HKMG layer includes a first portion disposed between the word line gate and one of the first insulation spacers and a second portion disposed between the word line gate and the substrate; and
forming drain regions in the substrate each disposed adjacent to one of the word line gates.

2. The method of claim 1 , wherein the first insulation layer is formed of a first insulation material, and the second insulation layer is formed of a second insulation material that is different from the first insulation material.

3. The method of claim 2 , wherein the first insulation material is silicon oxide, and the second insulation material is silicon nitride.

4. The method of claim 1 , further comprising:
forming silicide on upper surfaces of the erase gate and the control gates.

5. The method of claim 4 , further comprising:
forming silicide on an upper surface of the semiconductor substrate at the drain regions.

6. The method of claim 1 , wherein the word line gates are insulated from the substrate only by the layer of high K insulation material of the HKMG layer.

7. The method of claim 1 , further comprising:
forming a block of insulation material on each of the control gates, wherein the first insulation layer extends directly along side surfaces of each of the blocks of insulation material.

8. The method of claim 1 , wherein the forming of the erase gate and the word line gates includes:
forming a second polysilicon layer over the substrate and over the control gates;
removing portions of the second polysilicon layer over the control gates and over the substrate, leaving a first block of the second polysilicon layer between the control gates as the erase gate, leaving a second block of the second polysilicon layer adjacent to one of the first insulation spacers as one of the word line gates, and leaving a third block of the second polysilicon layer adjacent to another one of the first insulation spacers as another one of the word line gates.

Assignees

• Silicon Storage Tech Inc

Inventors

• Zhou Feng
• Liu Xian
• Yang Jeng-Wei
• Su Chien-Sheng
• Do Nhan

Classifications

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title