Modular, frequency-flexible, superconducting quantum processor architecture

Patent metadata

Field	Value
Publication number	US-11288587-B2
Application number	US-201916449239-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Jun 21, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A modular superconducting quantum processor includes a first superconducting chip including a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency, and a second superconducting chip including a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and to the second superconducting chip. The interposer chip has interposer coupler elements configured to couple the second plurality of qubits to the fourth plurality of qubits.

First claim

We claim:

1. A modular superconducting quantum processor, comprising:
a first superconducting chip comprising a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency;
a second superconducting chip comprising a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency; and
an interposer chip connected to said first superconducting chip and to said second superconducting chip, wherein the interposer chip comprises interposer coupler elements configured to couple the second plurality of qubits having substantially the second resonance frequency to the fourth plurality of qubits having substantially the second resonance frequency.

2. The modular superconducting quantum processor according to claim 1 , wherein the second plurality of qubits are arranged at a periphery in the first superconducting chip and the fourth plurality of qubits are arranged at a periphery of the second superconducting chip so as to enable coupling between the second plurality of qubits and the fourth plurality of qubits.

3. The modular superconducting quantum processor according to claim 1 , wherein the first superconducting chip further comprises a first plurality of coupling elements configured to couple the first plurality of qubits with the second plurality of qubits.

4. The modular superconducting quantum processor according to claim 1 , wherein the second superconducting chip further comprises a second plurality of coupling elements configured to couple the third plurality of qubits with the fourth plurality of qubits.

5. The modular superconducting quantum processor according to claim 1 , wherein the first superconducting chip and the second superconducting chip comprise readout elements to readout each of the first plurality of qubits, each of the second plurality of qubits, each of the third plurality of qubits or each of the fourth plurality of qubits or to readout any combination thereof.

6. The modular superconducting quantum processor according to claim 1 , wherein the first superconducting chip and the second superconducting chip comprises ground elements configured to connect ground planes of the first superconducting chip and the second superconducting chip.

7. The modular superconducting quantum processor according to claim 1 , wherein the interposer chip comprises ground elements configured to connect ground planes on the interposer chip.

8. The modular superconducting quantum processor according to claim 1 , wherein the interposer coupler elements are selected from the group consisting of a resonator, a direct capacitive coupler, and a frequency tunable element.

9. The modular superconducting quantum processor according to claim 1 , wherein the first plurality of qubits and the third plurality of qubits are arranged in frequency to implement cross-resonance (CR) gates.

10. The modular superconducting quantum processor according to claim 1 , wherein the second plurality of qubits and the fourth plurality of qubits comprise tunable gates or resonance induced phase (RIP) gates.

11. The modular superconducting quantum processor according to claim 1 , further comprising a substrate, wherein the first and second superconducting chips are mounted to the substrate and the first plurality of qubits, the second plurality of qubits, the third plurality of qubits, and the fourth plurality of qubits are connected to the substrate through a plurality of vias and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third and fourth plurality of qubits through the substrate.

12. The modular superconducting quantum processor according to claim 11 , wherein the first and second superconducting chips are mounted to the substrate so as to allow free access to the first, second, third and fourth plurality of qubits from a side of the first and second superconducting chips that is opposite a side of the first and second superconducting chips facing the substrate.

13. The modular superconducting quantum processor according to claim 11 , wherein the interposer chip is connected to the first and second superconducting chips and the substrate using solder bumps.

14. The modular superconducting quantum processor according to claim 1 , wherein the first superconducting chip, the second superconducting chip, and the interposer chip are configured and arranged to provide a modular system so as to enable direct accessibility to each of the first, second, third and fourth qubits.

15. The modular superconducting quantum processor according to claim 1 , further comprising:
a plurality of first superconducting chips comprising the first plurality of qubits and the second plurality of qubits;
a plurality of second superconducting chips comprising the third plurality of qubits and the fourth plurality of qubits,
wherein the interposer chip is configured to connect to said plurality of first superconducting chips and to said plurality of second superconducting chips.

16. A method of making a modular superconducting quantum processor, comprising:
providing a first superconducting chip, the first superconducting chip comprising a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency;
providing a second superconducting chip, the second superconducting chip comprising a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency;
providing an interposer chip comprising interposer coupler elements configured to couple the second plurality of qubits having substantially the second resonance frequency to the fourth plurality of qubits having substantially the second resonance frequency;
mounting the first superconducting chip and the second superconducting chip on a substrate; and
mounting the interposer chip on at least a portion of the first superconducting chip, on at least a portion of the second superconducting chip, and on at least a portion of the substrate such that the first plurality of qubits, the second plurality of qubits, the third plurality of qubits and the fourth plurality of qubits are accessible from a side opposite to a side facing the substrate.

17. The method according to claim 16 , further comprising conductively connecting the first plurality, the second plurality, the third plurality and the fourth plurality of qubits to the substrate and conductively connecting the interposer chip to the substrate and to the first superconducting chip and to the second superconducting chip.

18. The method according to claim 16 , wherein mounting the first superconducting chip and the second superconducting chip on the substrate comprises connecting the first, the second, the third and fourth plurality of qubits to the substrate using a plurality of vias in the first and second superconducting chips and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third and fourth plurality of qubits through the substrate.

19. The method according to claim 16 , further comprising

Assignees

• IBM

Inventors

• Paik Hanhee
• Nah Jae-Woong
• Andry Paul S
• Sandberg Martin O

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title