Computer-implemented method of designing a modularized stacked integrated circuit

Patent metadata

Field	Value
Publication number	US-9904751-B2
Application number	US-201514743066-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Jan 12, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.

First claim

What is claimed is:

1. A computer-implemented method of designing a stacked integrated circuit having an interposer and at least a first die disposed upon the interposer, wherein, a portion of the first die and a portion of the interposer have the same function, the method comprising:
providing a physical layout group, comprising:
a first layout corresponding to the first die having both a first function and a second function, the second function being different from the first function; and
a second layout corresponding to the interposer configured for the first die connected thereon;

partitioning the physical layout group into a first physical layout partition corresponding to the first function, wherein the first physical layout partition is composed of the portion of the first layout and the portion of the second layout having the first function;
performing a first automatic place-and-route (APR) process to obtain a first hierarchical layout according to the first physical layout partition;
verifying the first hierarchical layout to obtain a verified first hierarchical layout by using a first verification, wherein the verification of the portion of the first die and the portion of the interposer having the same function is performed in parallel;
partitioning the physical layout group into a second physical layout partition according to the second function;
performing a second automatic place-and-route (APR) process to obtain a second hierarchical layout according to the second physical layout partition;
performing a second verification on the second hierarchical layout; and
merging the first hierarchical layout and the second hierarchical layout to obtain a single physical layout of a stacked integrated circuit device comprising the first die, the second die and the interposer; and
performing a third verification on the single physical layout; and
fabricating the integrated circuit based on the verified first hierarchical layout.

2. The method as claimed in claim 1 , wherein the physical layout group comprises a third layout corresponding to the second function of a second die, wherein the second die has the first function and the second function, wherein the interposer is configured for the second die beside to the first die connected thereon, wherein the third layout has the first function and the second function.

3. The method as claimed in claim 2 , wherein the first die comprises a system on chip (SoC) die, and the second die comprises a memory die.

4. The method as claimed in claim 2 , wherein the physical layout group comprises a fourth layout corresponding to the second die having a sub-function of the first function, and wherein the fourth layout corresponds to the first layout.

5. The method as claimed in claim 4 , wherein first physical layout partition comprises the first layout, the fourth layout and a portion of the second layout.

6. The method as claimed in claim 2 , wherein the physical layout group comprises a fifth layout for a third die stacked on the second die having the second function.

7. The method as claimed in claim 6 , wherein second physical layout partition comprises the third layout, the fifth layout and a portion of the second layout.

8. The method as claimed in claim 1 , wherein the second layout comprises a placement design for through hole vias (TSVs) passing through the interposer.

9. The method as claimed in claim 1 , wherein the first layout comprises a placement design for bump structures of the first die, wherein the first die connects to the interposer through the bump structures.

10. The method as claimed in claim 1 , wherein the second physical layout partition comprises the third layout and a portion of the second layout.

11. The method as claimed in claim 1 , wherein performing the first, second and third verifications comprises performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS).

Assignees

• Mediatek Inc

Inventors

• Fang Jia Wei

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title