Cryogenic electronic packages and methods for fabricating cryogenic electronic packages

Patent metadata

Field	Value
Publication number	US-2018102469-A1
Application number	US-201715684337-A
Country	US
Kind code	A1
Filing date	Aug 23, 2017
Priority date	Oct 11, 2016
Publication date	Apr 12, 2018
Grant date	—

Abstract

A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

First claim

What is claimed is:

1 . A cryogenic electronic package, comprising:
a first superconducting multi-chip module (SMCM) having first and second opposing surfaces; a first superconducting interposer having first and second opposing surfaces, wherein the first surface of the first interposer is disposed over and coupled to the second surface of the first SMCM; a second SMCM having first and second opposing surfaces, wherein the first surface of the second SMCM is disposed over and coupled to the second surface of the first interposer; and a first superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the first superconducting semiconductor structure is disposed over and coupled to the second surface of the second SMCM, and the second SMCM and the first superconducting semiconductor structure are electrically coupled to the first SMCM through the first interposer.

2 . The cryogenic electronic package of claim 1 further comprising:
one or more first interconnect structures disposed between the second surface of the first SMCM and the first surface of the first interposer and coupled to form one or more electrical connections between the first interposer and the first SMCM; and
one or more second interconnect structures disposed between the second surface of the second SMCM and the first surface of the first superconducting semiconductor structure and coupled to form one or more electrical connections between the first superconducting semiconductor structure and the second SMCM, wherein the first interconnect structures have first dimensions and a first pad pitch, and the second interconnect structures have second dimensions and a second pad pitch, wherein the second dimensions are substantially less than the first dimensions, and the second pad pitch is substantially less than the first pad pitch.

3 . The cryogenic electronic package of claim 2 wherein each of the first and second interconnect structures includes a plurality of interconnect sections, and at least one of the interconnect sections includes a superconducting and/or a partially superconducting material.

4 . The cryogenic electronic package of claim 3 wherein the plurality of interconnect sections includes three interconnect sections, and at least two of the interconnect sections include a plurality of conductive layers, each of the conductive layers including a respective metal or alloy material or combination of materials that is different from other ones of the conductive layers, and each of the conductive layers having a respective melting point that is different from other ones of the conductive layers.

5 . The cryogenic electronic package of claim 2 wherein the first SMCM includes one or more interconnect pads disposed or otherwise provided on at least the second surface of the first SMCM, and the first interposer includes one or more interconnect pads disposed or otherwise provide on at least the first surface of the first interposer, wherein the first interconnect structures are electrically coupled to respective ones of the interconnect pads of the first SMCM and the first interposer.

6 . The cryogenic electronic package of claim 5 wherein at least one of the interconnect pads of the first SMCM and the first interposer includes a superconducting and/or a partially superconducting material.

7 . The cryogenic electronic package of claim 5 wherein the first interposer further includes one or more conventional and/or superconducting and/or partially superconducting metal through via structures, each of the through via structures including a first pad interconnect, a second pad interconnect and a through via, wherein the first and second pad interconnects each extend from selected portions of the first surface of the first interposer to selected portions of the second surface of the first interposer, and the through via is disposed or otherwise provided in a cavity formed between the first and second pad interconnects, wherein the through via structures are electrically coupled to respective ones of the interconnect pads of the first interposer.

8 . The cryogenic electronic package of claim 2 wherein the second MCM includes one or more interconnect pads disposed on at least the second surface of the second SMCM, and the first superconducting semiconductor structure includes one or more interconnect pads disposed on at least the first surface of the first superconducting semiconductor structure, wherein the second interconnect structures are electrically coupled to respective ones of the interconnect pads of the second SMCM and the first superconducting semiconductor structure.

9 . The cryogenic electronic package of claim 8 wherein at least one of the interconnect pads of the second SMCM and the first superconducting semiconductor structure includes a superconducting and/or a partially superconducting material.

10 . The cryogenic electronic package of claim 2 further comprising:
a first adhesive layer disposed between the second surface of the first interposer and the first surface of the second SMCM and coupled to form one or more electrical connections between the second SMCM and the first interposer.

11 . The cryogenic electronic package of claim 10 further comprising:
one or more wire and/or ribbon and/or spring bonding structures, wherein at least one of the bonding structures has a first portion electrically coupled to the second surface of the first interposer, and a second opposing portion electrically coupled to the second surface of the second SMCM to form one or more electrical connections between the second SMCM and the first interposer.

12 . The cryogenic electronic package of claim 1 further comprising:
a second superconducting interposer having first and second opposing surfaces, wherein the first surface of the second interposer is disposed over and coupled to the second surface of the first SMCM;
a third SMCM having first and second opposing surfaces, wherein the first surface of the third SMCM is disposed over and coupled to the second surface of the second interposer; and
a second superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the second superconducting semiconductor structure is disposed over and coupled to the second surface of the third SMCM, and the third SMCM and the second superconducting semiconductor are electrically coupled to the first SMCM through the second interposer, wherein the cryogenic electronic package creates a maximum possible superconducting path between the first and second superconducting semiconductor structures when the first and second superconducting semiconductor structures are electrically coupled with each other through the second SMCM, the first interposer, the first SMCM, the second interposer and the third SMCM.

13 . The cryogenic electronic package of claim 1 further comprising:
a third SMCM having first and second opposing surfaces, wherein the first surface of the third SMCM is disposed over and coupled to the second surface of the first interposer; and
a second superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the second superconducting semiconductor structure is disposed over and coupled to the second surface of the third SMCM, and the third SMCM and the second superconducting semiconductor are electrically coupled to the first SMCM through the first interposer, wherein the cryogenic electronic package creates a maximum possible superconducting path between the first and second superconducting semiconductor structures when t

Assignees

• Massachusetts Inst Technology

Inventors

• Das Rabindra N
• Dauler Eric A

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title