Microwave integrated quantum circuits with VIAS and methods for making the same

Patent metadata

Field	Value
Publication number	US-9971970-B1
Application number	US-201615140232-A
Country	US
Kind code	B1
Filing date	Apr 27, 2016
Priority date	Apr 27, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A quantum computing system includes a quantum circuit device, a substrate having a first surface on which the quantum processing device is disposed, and one or more vias each extending through the substrate. The vias include a material that is a superconducting material during operation of the quantum computing system.

First claim

What is claimed is:

1. A quantum computing system comprising:
a quantum circuit device having at least one operating frequency;
a first substrate having a first surface on which the quantum circuit device is disposed; and
electrically conducting vias each extending through the first substrate outside of a footprint of the quantum circuit device,
wherein the vias are arranged to suppress propagation of electromagnetic waves that have frequencies below a cutoff frequency, the cutoff frequency being larger than the operating frequency;
a set of three or more other electrically conducting vias each extending through the first substrate outside of the footprint of the quantum circuit device, wherein the other electrically conducting vias form respective vertices of a polygon; and
a signal line that includes a first via that extends through the first substrate and is inscribed in the polygon, wherein the signal line is electromagnetically coupled with the quantum circuit device to carry, during operation of the quantum computing system, a control signal to, or a readout signal from, the quantum circuit device.

2. The quantum computing system of claim 1 , further comprising
a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and
an electrically conducting layer that covers at least a portion of the recess of the second substrate,
wherein the recess of the second substrate is configured to suppress inside the recess propagation of the electromagnetic waves that have frequencies below the cutoff frequency.

3. The quantum computing system of claim 2 , further comprising another quantum circuit device having at least one other operating frequency, the other quantum circuit device being disposed on the first surface of the first substrate and spaced apart from the quantum circuit device.

4. The quantum computing system of claim 3 , further comprising other electrically conductive vias each extending through the first substrate outside of a footprint of the other quantum circuit device, wherein the other vias are arranged to suppress propagation of electromagnetic waves that have frequencies below another cutoff frequency, the other cutoff frequency being larger than the other operating frequency.

5. The quantum computing system of claim 4 , further comprising a coupling line that includes an electrical conductor extending along the first surface of the first substrate, wherein the other quantum circuit device is electromagnetically coupled with the quantum circuit device through the coupling line, through a capacitive coupling, or through an inductive coupling.

6. The quantum computing system of claim 5 , wherein the first surface of the second substrate defines another recess of the second substrate, the first and second substrates being further arranged such that the other recess of the second substrate forms another enclosure that houses the other quantum circuit device, the electrically conducting layer further covers at least a portion of the other recess of the second substrate, and the other recess of the second substrate is configured to suppress inside the other recess propagation of the electromagnetic waves that have frequencies below the other cutoff frequency.

7. The quantum computing system of claim 6 , wherein the first surface of the second substrate defines a third recess, the third recess forming an enclosure that hosts the coupling line.

8. The quantum computing system of claim 2 , wherein the electrically conducting layer is grounded during operation of the quantum computing system.

9. The quantum computing system of claim 2 , wherein the electrically conducting layer is a superconducting layer during operation of the quantum computing system.

10. The quantum computing system of claim 2 , wherein the second substrate comprises a lithographically defined thick photoresist.

11. The quantum computing system of claim 2 , wherein the second substrate comprises one of silicon, sapphire, silicon oxide, silicon nitride, quartz, lithographically defined thick photoresist or an electrical conducting material that is a superconducting material when the quantum computing system is operated.

12. The quantum computing system of claim 1 , further comprising:
a DC pad disposed on the first surface of the first substrate and electromagnetically coupled with the quantum circuit device; and
a DC line that includes one or more vias that extend through the first substrate and contact the DC pad, wherein the DC line carries, during operation of the quantum computing system, a DC signal to and from the quantum circuit device.

13. The quantum computing system of claim 1 , wherein at least some of the electrically conductive vias are grounded during operation of the quantum computing system.

14. The quantum computing system of claim 1 , wherein the electrically conducting vias comprise a material that is a superconducting material during operation of the quantum computing system.

15. The quantum computing system of claim 1 , wherein the quantum circuit device is one of a qubit, a tunable quantum coupler, a readout circuit including one or more linear resonators or one or more nonlinear resonators, a filter, a quantum amplifier, or a circulator.

16. The quantum computing system of claim 1 , wherein the first substrate comprises a low-loss material.

17. The quantum computing system of claim 1 , wherein the first substrate comprises silicon oxide.

18. A quantum computing system comprising:
a quantum circuit device having at least one operating frequency;
a first substrate having a first surface on which the quantum circuit device is disposed; and
electrically conducting vias each extending through the first substrate outside of a footprint of the quantum circuit device,
wherein the vias are arranged to suppress propagation of electromagnetic waves that have frequencies below a cutoff frequency, the cutoff frequency being larger than the operating frequency;
a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device;
an electrically conducting layer that covers at least a portion of the recess of the second substrate,
wherein the recess of the second substrate is configured to suppress inside the recess propagation of the electromagnetic waves that have frequencies below the cutoff frequency;
another quantum circuit device having at least one other operating frequency;
a third substrate having a first surface onto which the other quantum circuit device is disposed; and
other electrically conductive vias each extending through the third substrate outside of a footprint of the other quantum circuit device, the other vias being arranged to suppress, across a volume of the third substrate that is adjacent to the footprint of the other quantum circuit device, propagation of electromagnetic waves that have frequencies below another cutoff frequency, the other cutoff frequency being larger than the other operating frequency,
wherein the first substrate (i) has a second surface opposing the first surface that defines a recess of the first substrate, and (ii) is sandwiched between the second substrate and the third substrate, the first and third substrates being arranged such that the recess of the first subs

Assignees

• Rigetti & Co Inc
• Rigetti & Co Inc

Inventors

• Rigetti Chad T
• Vahidpour Mehrnoosh
• Thompson Dane Christoffer
• Marchenokov Alexei N
• Sete Eyob Alebachew
• Reagor Matthew J

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title