Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Patent metadata

Field	Value
Publication number	US-9527723-B2
Application number	US-201514643074-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Mar 13, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

First claim

What is claimed:

1. A semiconductor device, comprising:
a first semiconductor die;
a modular interconnect structure including a conductive via disposed laterally adjacent to the first semiconductor die;
an encapsulant deposited between the first semiconductor die and the modular interconnect structure;
a conductive layer formed over the first semiconductor die and modular interconnect structure; and
a second semiconductor die disposed over the conductive layer, wherein the second semiconductor die includes a microelectromechanical system.

2. The semiconductor device of claim 1 , further including an interconnect structure formed over the modular interconnect structure opposite the conductive layer.

3. The semiconductor device of claim 1 , wherein an active area of the first semiconductor die remains devoid of the conductive layer.

4. The semiconductor device of claim 1 , wherein the first semiconductor die includes a microelectromechanical system.

5. The semiconductor device of claim 1 , further including an interposer disposed between the first semiconductor die and the second semiconductor.

6. The semiconductor device of claim 1 , wherein the second semiconductor die is disposed with an active surface oriented toward the first semiconductor die.

7. A semiconductor device, comprising:
a first semiconductor die;
a modular interconnect structure disposed laterally adjacent to the first semiconductor die;
a first interconnect structure including a conductive layer and an insulating layer formed over the first semiconductor die and modular interconnect structure with an active region of the first semiconductor die devoid of the first interconnect structure; and
a second semiconductor die disposed over the first semiconductor die, wherein the second semiconductor die includes a microelectromechanical system.

8. The semiconductor device of claim 7 , wherein the second semiconductor die is mounted to the first interconnect structure by a bump.

9. The semiconductor device of claim 7 , wherein the second semiconductor die is covered by a rigid lid comprising a sacrificial base material selected from the group consisting of silicon, polymer, beryllium oxide, glass, copper, aluminum, ferrite, carbonyl iron, stainless steel, nickel, silver, low carbon steel, silicon-iron steel, and conductive resin.

10. The semiconductor device of claim 7 , further including an encapsulant deposited between the first semiconductor die and modular interconnect structure.

11. The semiconductor device of claim 7 , wherein the second semiconductor die is disposed with an active surface oriented toward the first semiconductor die.

12. The semiconductor device of claim 7 , further including an interposer disposed over the first semiconductor die, the second semiconductor die disposed over the interposer.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Choi Won Kyoung
• Chen Kang
• Micallef Ivan

Classifications

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

• B81B2207/098

  Arrangements not provided for in groups B81B2207/092 - B81B2207/097 · CPC title

• B81B2207/092

  Buried interconnects in the substrate or in the lid · CPC title

• B81B7/007 Primary

  Interconnections between the MEMS and external electrical signals · CPC title

• B81C1/00301

  Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias · CPC title