Microwave integrated quantum circuits with interposer

Patent metadata

Field	Value
Publication number	US-9836699-B1
Application number	US-201615140261-A
Country	US
Kind code	B1
Filing date	Apr 27, 2016
Priority date	Apr 27, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A quantum computing apparatus, including a quantum circuit device; and an interposer including a connectorization layer including a plurality of terminals for connecting the quantum computing apparatus to a corresponding plurality of cables and a plurality of signal lines electrically coupled, via electrical contacts, to the plurality of terminals; and at least one intermediate layer between the quantum circuit device and the connectorization layer, the at least one intermediate layer comprising an integrated circuit layer, the at least one intermediate layer being electrically coupled to the signal lines of the interposer. The interposer is configured to supply the quantum circuit device, during operation of the quantum computing apparatus, at least control signals and readout signals to and from the plurality of cables.

First claim

What is claimed is:

1. A quantum computing apparatus, comprising:
a quantum circuit device; and
an interposer comprising:
a connectorization layer comprising a plurality of terminals for connecting the quantum computing apparatus to a corresponding plurality of cables and a plurality of signal lines electrically coupled, via electrical contacts, to the plurality of terminals; and
at least one intermediate layer between the quantum circuit device and the connectorization layer, the at least one intermediate layer comprising an integrated circuit layer, the at least one intermediate layer being electrically coupled to the signal lines of the interposer,
wherein the interposer is configured to supply the quantum circuit device, during operation of the quantum computing apparatus, at least control signals and readout signals to and from the plurality of cables.

2. The quantum computing apparatus of claim 1 , wherein the integrated circuit layer is integrated with the quantum circuit device.

3. The quantum computing apparatus of claim 2 , wherein the quantum circuit device comprises a circuit wafer supporting a quantum circuit and the integrated circuit layer is wafer bonded to the circuit wafer.

4. The quantum computing apparatus of claim 2 , wherein the quantum circuit device comprises a circuit wafer supporting a quantum circuit and the integrated circuit layer comprises a substrate bonded to the circuit wafer.

5. The quantum computing apparatus of claim 4 , wherein the substrate is a printed circuit board (PCB), polyimide, or a ceramic layer.

6. The quantum computing apparatus of claim 4 , wherein the substrate is a silicon or a sapphire substrate.

7. The quantum computing apparatus of claim 1 , wherein the integrated circuit layer of the intermediate layers comprises a directional coupling circuit.

8. The quantum computing apparatus of claim 1 , wherein the integrated circuit layer of the intermediate layers comprises a quantum amplifier circuit.

9. The quantum computing apparatus of claim 1 , wherein the integrated circuit layer of the intermediate layers comprises a multiplexing circuit.

10. The quantum computing apparatus of claim 1 , wherein the integrated circuit layer comprises a circulator circuit or an isolator circuit.

11. The quantum computing apparatus of claim 1 , further comprising a plurality of bonding elements each connecting a corresponding electrical contact on a surface of the one or more intermediate layers with an electrical contact on a surface of the quantum circuit device.

12. The quantum computing apparatus of claim 11 , wherein each bonding element is formed from a bonding ball or bonding bump during a flip chip process.

13. The quantum computing apparatus of claim 1 , wherein at least one of the intermediate layers comprises vias each electrically coupling an electrical contact on one side of the layer with a corresponding electrical contact on the opposite side of the layer.

14. The quantum computing apparatus of claim 1 , wherein the quantum circuit device comprises a circuit wafer supporting a quantum circuit and the one or more intermediate layers comprise a material having a coefficient of thermal expansion (CTE) that substantially matches a CTE of the circuit wafer.

15. The quantum computing apparatus of claim 14 , wherein the material is different from a material of the circuit wafer.

16. The quantum computing apparatus of claim 15 , wherein the material is selected from the group consisting of BeO, Al 2 O 3 , AlN, Quartz and Sapphire.

17. The quantum computing apparatus of claim 14 , wherein the material is the same as a material of the circuit wafer.

18. The quantum computing apparatus of claim 11 , wherein the bonding elements comprise conductive metals.

19. The quantum computing apparatus of claim 1 , wherein the one or more intermediate layers comprise an electrically conductive film.

20. The quantum computing apparatus of claim 19 , wherein the electrically conductive film is formed from a material selected from the group consisting of indium, aluminum, copper, silver, or tin.

21. The quantum computing apparatus of claim 1 , wherein the quantum circuit device comprises a circuit wafer and the interposer comprises an interposer material that is the same as a material of the circuit wafer.

22. The quantum computing apparatus of claim 1 , wherein the interposer comprises through hole vias coated with an electrically conductive film.

23. The quantum computing apparatus of claim 1 , wherein the interposer comprises a printed circuit board (PCB).

24. The quantum computing apparatus of claim 23 , wherein the PCB supports the signal lines which are wire bonded to electrical contacts on the quantum circuit device or the integrated circuit layer.

25. The quantum computing apparatus of claim 24 , wherein the PCB has one or more physical holes acting as pass-throughs for the wire bonds from the signal lines of the PCB to the electrical contacts on the quantum circuit device or the integrated circuit layer.

26. The quantum computing apparatus of claim 25 , wherein the wire bonds from the signal lines of the PCB to the electrical contacts on the quantum circuit device or the integrated circuit layer form (i) a connection for DC signals and MW signals, or (ii) a ground connection.

27. The quantum computing apparatus of claim 1 , wherein the connectorization layer comprises an electrically conductive metal.

28. The quantum computing apparatus of claim 27 , wherein the electrically conductive metal is aluminum, copper or molybdenum.

29. The quantum computing apparatus of claim 1 , wherein the connectorization layer comprises a printed circuit board (PCB).

30. The quantum computing apparatus of claim 1 , wherein the interposer comprises a substrate attached to the connectorization layer by a layer of epoxy or eccosorb.

31. The quantum computing apparatus of claim 1 , wherein the interposer comprises a substrate coupled to the connectorization layer via alignment pins and registration marks.

32. The quantum computing apparatus of claim 1 , wherein the interposer comprises a substrate and a thinnerposer positioned between the substrate and the connectorization layer.

33. The quantum computing apparatus of claim 32 , wherein the thinnerposer comprises one or more compressible electrical contacts.

34. The quantum computing apparatus of claim 33 , wherein the compressible electrical contacts comprise fuzz buttons.

35. The quantum computing apparatus of claim 33 , wherein the compressible electrical contacts comprise a metal wool.

36. The quantum computing apparatus of claim 33 , wherein the compressible electrical contacts are registered with corresponding electrical contacts on an adjacent surface of the substrate.

37. The quantum computing apparatus of claim 33 , wherein the compressible electrical contacts are registered with corresponding electrical contacts on an adjacent surface of the connectorization layer.

38. A method of forming an assembly for a quantum computing apparatus, the method comprising:
attaching an interposer to a circuit wafer for a quantum circuit device, the interposer comprising an integrated circuit layer and a connect

Assignees

• Rigetti & Co Inc
• Rigetti & Co

Inventors

• Rigetti Chad Tyler
• Vahidpour Mehrnoosh
• Thompson Dane Christoffer
• Orgiazzi Jean-Luc François-Xavier
• Caldwell Shane
• Maydra Richard
• Selvanayagam Michael

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• Y10S977/933

  Spintronics or quantum computing · CPC title

• G06N99/002 Primary

  Physics · mapped topic

• H01L39/2493

  Electricity · mapped topic

• H01L39/223

  Electricity · mapped topic