Ferroelectric memory devices employing conductivity modulation of a thin semiconductor material or a two-dimensional charge carrier gas and methods of operating the same

Patent metadata

Field	Value
Publication number	US-11271009-B2
Application number	US-202016886179-A
Country	US
Kind code	B2
Filing date	May 28, 2020
Priority date	Dec 20, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

First claim

What is claimed is:

1. A ferroelectric memory device comprising:
a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer;
a ferroelectric memory element located adjacent to a first surface of the two-dimensional semiconductor material layer; and
a conductive gate electrode located adjacent to the ferroelectric memory element,
wherein the two-dimensional semiconductor material layer has a greater lateral extent along a direction parallel to an interface between the two-dimensional semiconductor material layer and the ferroelectric memory element than the ferroelectric memory element.

2. The ferroelectric memory device of claim 1 , wherein:
the two-dimensional semiconductor material layer includes the two-dimensional charge carrier gas layer which comprises a two-dimensional electron gas (2DEG) layer;
the ferroelectric memory element contacts the first surface of the two-dimensional semiconductor material layer; and
the conductive gate electrode contacts the ferroelectric memory element.

3. The ferroelectric memory device of claim 2 , wherein the ferroelectric memory element comprises a ferroelectric dielectric material.

4. The ferroelectric memory device of claim 2 , wherein the ferroelectric dielectric material is selected from barium titanate, colemanite, bismuth titanate, europium barium titanate, ferroelectric polymer, germanium telluride, langbeinite, lead scandium tantalate, lead titanate, lead zirconate titanate, lithium niobate, polyvinylidene fluoride, potassium niobate, potassium sodium tartrate, potassium titanyl phosphate, sodium bismuth titanate, ammonium dihydrogen phosphate, potassium dihydrogen phosphate KH 2 PO 4 (KDP), lithium tantalate, lead lanthanum titanate, and lead lanthanum zirconate titanate.

5. The ferroelectric memory device of claim 2 , further comprising:
a backside ferroelectric memory element in contact with a second surface of the two-dimensional semiconductor material layer that is located on an opposite side of the first surface of the two-dimensional semiconductor material layer;
a conductive backside gate electrode in contact with the backside ferroelectric memory element; and
an electrically conductive path connecting the conductive backside gate electrode and the conductive gate electrode.

6. The ferroelectric memory device of claim 2 , further comprising a backside contact electrode located adjacent to a second surface of the two-dimensional semiconductor material layer that is located on an opposite side of the first surface of the two-dimensional semiconductor material layer.

7. The ferroelectric memory device of claim 1 , wherein:
the two-dimensional semiconductor material layer has a thickness in a range from 0.3 nm to 10 nm; and
the two-dimensional semiconductor material layer comprises a two-dimensional charge carrier gas layer that is located within 10 nm from a two-dimensional Euclidian plane that includes an interface between the two-dimensional semiconductor material layer and the ferroelectric memory element.

8. The ferroelectric memory device of claim 1 , wherein the two-dimensional semiconductor material layer has the thickness of 1 to 5 monolayers of atoms of the semiconductor material.

9. The ferroelectric memory device of claim 1 , wherein each of the conductive gate electrode comprises a metallic contact material selected from a metal-semiconductor compound, a conductive metallic nitride, an elemental metal, and an intermetallic alloy material.

10. The ferroelectric memory device of claim 1 , wherein the two-dimensional semiconductor material layer comprises fluorinated graphene.

11. The ferroelectric memory device of claim 1 , wherein the two-dimensional semiconductor material layer comprises hexagonal boron nitride.

12. The ferroelectric memory device of claim 1 , wherein the two-dimensional semiconductor material layer comprises molybdenum disulfide.

13. The ferroelectric memory device of claim 1 , wherein the two-dimensional semiconductor material layer comprises germanane.

14. A ferroelectric memory array comprising an array of the ferroelectric memory devices of claim 1 .

15. The ferroelectric memory device of claim 1 , wherein the ferroelectric memory device comprises a source contact that contacts a first surface segment of the two-dimensional semiconductor material layer and does not directly contact the ferroelectric memory element, and a drain contact that contacts a second surface segment of the two-dimensional semiconductor material layer and does not directly contact the ferroelectric memory element.

16. The ferroelectric memory device of claim 15 , wherein:
the interface between the two-dimensional semiconductor material layer and the ferroelectric memory element comprises a segment of a top surface of the two-dimensional semiconductor material layer;
the first surface segment is a first additional segment of the top surface of the two-dimensional semiconductor material layer; and
the second surface segment is a second additional segment of the top surface of the two-dimensional semiconductor material layer.

17. The ferroelectric memory device of claim 15 , wherein:
the interface between the two-dimensional semiconductor material layer and the ferroelectric memory element comprises a segment of a top surface of the two-dimensional semiconductor material layer;
the first surface segment and the second surface segment comprise portions of sidewalls of the two-dimensional semiconductor material layer that are different from, and are adjoined to, the top surface of two-dimensional semiconductor material layer.

18. A ferroelectric memory device comprising:
a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, and having a first planar surface and a second planar surface that are parallel to each other,
a ferroelectric memory element located on the first surface of the two-dimensional semiconductor material layer;
a conductive gate electrode located adjacent to the ferroelectric memory element; and
a backside contact electrode located directly on the second surface of the two-dimensional semiconductor material layer.

Assignees

• Sandisk Technologies Llc

Inventors

• Kalitsov Alan
• Stewart Derek
• Bedau Daniel
• Bertero Gerardo

Classifications

• H10D64/689 Primary

  having ferroelectric layers · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D30/47

  having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title