Three-dimensional memory device having a transition metal dichalcogenide channel

Patent metadata

Field	Value
Publication number	US-9721963-B1
Application number	US-201615094552-A
Country	US
Kind code	B1
Filing date	Apr 8, 2016
Priority date	Apr 8, 2016
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A monolithic three-dimensional memory device contains a high mobility metal dichalcogenide channel. A stack of alternating layers comprising first material layers and second material layers is formed over a substrate. A memory opening is formed through the stack of alternating layers. A memory film is formed in the memory opening. A metal dichalcogenide channel is formed on an inner sidewall of the memory film. A dielectric core is formed within the metal dichalcogenide channel. A stack of titanium and gold may be employed to form a drain region to enhance contact. A hafnium oxide, aluminum oxide or hafnium aluminum oxide hafnium aluminum oxide layer may be employed on either side, or on both sides, of the metal dichalcogenide channel to enhance the mobility of electrons in the metal dichalcogenide channel.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a memory opening vertically extending through the stack of alternating layers;
a memory film located at a periphery of the memory opening;
a metal dichalcogenide channel extending through the memory opening and located inside the memory film; and
a drain region contacting at least one of an upper end and a sidewall of the metal dichalcogenide channel,
wherein the monolithic three-dimensional memory device comprises at least one feature selected from:
a first feature that the drain region further comprises an annular doped metal dichalcogenide drain portion;
a second feature that the drain region contacts the upper end of the metal dichalcogenide channel; and
a third feature that the drain region contacts the sidewall of the metal dichalcogenide channel.

2. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device comprises the second feature.

3. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device comprises the third feature.

4. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device comprises the first feature.

5. The monolithic three-dimensional memory device of claim 4 , wherein the drain region further comprises at least one metal or metal alloy layer surrounded by the annular doped metal dichalcogenide drain portion to provide an Ohmic contact with the annular doped metal dichalcogenide drain portion.

6. The monolithic three-dimensional memory device of claim 5 , wherein the at least one metal or metal alloy layer comprises at least one of Ti, Au, Ni, In and alloys thereof.

7. The monolithic three-dimensional memory device of claim 4 , wherein the drain region further comprises:
a stack of a first metal layer and a second metal layer surrounded by the annular doped metal dichalcogenide drain portion; and
a doped semiconductor drain portion surrounded by the stack of the first metal layer and the second metal layer.

8. The monolithic three-dimensional memory device of claim 4 , wherein the drain region further comprises a doped semiconductor drain portion contacting an inner sidewall of the annular doped metal dichalcogenide drain portion.

9. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a memory opening vertically extending through the stack of alternating layers;
a memory film located at a periphery of the memory opening; and
a metal dichalcogenide channel extending through the memory opening and located inside the memory film,
wherein the monolithic three-dimensional memory device comprises at least one feature selected from:
a first feature that the monolithic three-dimensional memory device further comprises a single crystal silicon epitaxial channel portion that is located at a lower end of the memory opening and epitaxially aligned to a semiconductor material layer of the substrate, wherein the metal dichalcogenide channel contacts a top surface of the epitaxial channel portion;
a second feature that the memory film comprises, from outside to inside, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, and an innermost layer of the tunneling dielectric layer comprises a high-k dielectric material having a dielectric constant greater than 7.9;
a third feature that the monolithic three-dimensional memory device further comprises a dielectric core located inside the metal dichalcogenide channel, and an interfacial dielectric layer comprising a high-k dielectric material having a dielectric constant greater than 7.9 and contacting an inner sidewall of the metal dichalcogenide channel and an outer sidewall of the dielectric core;
a fourth feature that the metal dichalcogenide channel comprises 1 to 8 molecular monolayers of Mo 1−x W x S 2−y−z Se y Te z , wherein x is a number in a range from, and including, 0 to, and including 1, y is a number in a range from, and including, 0 and to, and including, 2, and z is a number in a range from, and including, 0 and to, and including, 2, wherein the metal dichalcogenide channel comprises 1 molecular monolayer to 3 molecular monolayers of Mo 1−x W x S 2−y Se y , which provides a two-dimensional electron gas with quantum confinement along a radial direction of the memory opening, the molecular monolayer comprises a metal atomic monolayer located between first and second chalcogen atomic monolayers, the metal atoms in the molecular monolayer are bound to chalcogen atoms in the molecular monolayer by intra molecular monolayer covalent bonds, and the molecular monolayers are bound to adjacent molecular monolayers by inter molecular monolayer van der Waals forces which are weaker than the intra molecular monolayer covalent bonds; and
a fifth feature that:
the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, respective word lines of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional array of NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of metal dichalcogenide channels, wherein at least one end portion of each of the plurality of metal dichalcogenide channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of metal dichalcogenide channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

10. The monolithic three-dimensional memory device of claim 9 , wherein the monolithic three-dimensional memory device comprises the first feature.

11. The monolithic three-dimensional memory device of claim 9 , wherein the monolithic three-dimensional memory device comprises the fourth feature.

12. The monolithic three-dimensional memory device of claim 9 , wherein the monolithic three-dimensional memory device comprises the fifth feature.

13. The monolithic three-dimensional memory device of claim 9 , wherein the monolithic three-dimensional memory device comprises the second feature.

14. The monolithic three-dimensional memory device of claim 13 , wherein the high-k dielectric material comprises aluminum oxide, hafnium oxide or hafnium aluminum oxide.

15. The monolithic three-dimensional memory device of claim 9 , wherein the monolithic three-dimensional memory device comprises the third feature.

16. The monolithic three-di

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Rabkin Peter
• Higashitani Masaaki

Classifications

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic