Three-dimensional ferroelectric memory device and method of making thereof

Patent metadata

Field	Value
Publication number	US-9941299-B1
Application number	US-201715604092-A
Country	US
Kind code	B1
Filing date	May 24, 2017
Priority date	May 24, 2017
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A three-dimensional memory device includes an alternating stack of word lines and insulating layers, vertical semiconductor channels vertically extending through the alternating stack, and a ferroelectric memory material located between each vertical semiconductor channel and the word lines.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack located over a substrate, wherein the alternating stack comprises alternating insulating layers and electrically conductive layers, and wherein the electrically conductive layers comprise word lines of the three-dimensional memory device;
vertical semiconductor channels vertically extending through the alternating stack; and
ferroelectric memory elements located between each vertical semiconductor channel and the electrically conductive layers of the alternating stack,

wherein:
the ferroelectric memory elements comprise ferroelectric material liners located in the alternating stack;
a combination of each ferroelectric material liner and each electrically conductive layer in the alternating stack comprises a combined spacer;
the alternating stack comprises alternating insulating layers and combined spacers; and
each of the vertical semiconductor channels contacts each of the ferroelectric material liners, and wherein the three-dimensional memory device comprises at least one feature selected from:
a first feature that the three-dimensional memory device further comprises:
a semiconductor material layer located on or within the substrate, wherein each of the vertical semiconductor channels contacts the semiconductor material layer,
a source region located in, or on, the semiconductor material layer and laterally offset from the vertical semiconductor channels, and
drain regions located at an upper end of each of the vertical semiconductor channels;

a second feature that the alternating stack comprises a terrace region in which each combined spacer except a topmost combined spacer laterally extends farther away from the vertical semiconductor channels than overlying combined spacers, and the three-dimensional memory device further comprises a plurality of contact via structures contacting a top surface of a respective one of the electrically conductive layers within the terrace region; and
a third feature that the ferroelectric material liners comprise an orthorhombic metal oxide whose unit cell has a non-zero permanent electric dipole moment.

2. The three-dimensional memory device of claim 1 , wherein each of the ferroelectric material liners comprises:
an upper horizontal portion contacting a top surface of one of the electrically conductive layers;
a lower horizontal portion contacting a bottom surface of the one of the electrically conductive layers; and
a plurality of vertically extending cylindrical portions that laterally surrounds, and contacts, a respective one of the vertical semiconductor channels and vertically connecting the upper horizontal portion and the lower horizontal portion.

3. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the first feature.

4. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the second feature.

5. The three-dimensional memory device of claim 4 , further comprising a retro-stepped dielectric material portion overlying, and contacting, surfaces of the ferroelectric material liner in the terrace region,
wherein:
the plurality of contact via structures extends through the retro-stepped dielectric material portion and a respective one of the ferroelectric material liners; and
each of the electrically conductive layers is vertically spaced from the retro-stepped dielectric material portion by a horizontal portion of a respective one of the ferroelectric material liners, and is laterally spaced from the retro-stepped dielectric material portion by a vertical portion of the respective one of the ferroelectric material liners.

6. The three-dimensional memory device of claim 1 , wherein each of the vertical semiconductor channels directly contacts a sidewall of each of the insulating layers of the alternating stack and a sidewall of each of the ferroelectric material liners in the alternating stack, and is laterally spaced from each of the electrically conductive layers by a respective one of the ferroelectric material liners.

7. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the third feature.

8. The three-dimensional memory device of claim 7 , wherein the orthorhombic metal oxide comprises an orthorhombic hafnium doped zirconium oxide or an orthorhombic hafnium oxide doped with a dopant having an atomic radius that is between 40% smaller to 15% larger than the atomic radium of hafnium.

9. The three-dimensional memory device of claim 8 , wherein:
the orthorhombic metal oxide comprises an orthorhombic hafnium oxide doped with at least one of silicon, aluminum, yttrium, gadolinium and zirconium;
each of the ferroelectric material liners is a conformal material layer having a thickness variation that is less than 30% from an average thickness; and
an average thickness of the ferroelectric material liners is in a range from 5 nm to 30 nm.

10. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming vertical semiconductor channels through the alternating stack; and
replacing the sacrificial material layers with combined spacers, each of which comprises a ferroelectric liner and an electrically conductive layer, after forming the vertical semiconductor channels,
wherein the method comprises at least one feature selected from:
a first feature that the method further comprises: forming a backside trench through the alternating stack of the insulating layers and the sacrificial material layers, and removing the sacrificial material layers by providing an etchant that etches the sacrificial material layers selective to the insulating layers through the backside trench, wherein backside recesses are formed in volumes from which the sacrificial material layers are removed, wherein the combined spacers are formed in the backside recesses;
a second feature that the method further comprises: patterning the alternating stack to form a terrace region in which each sacrificial material layer except a topmost sacrificial material layer has a greater lateral extent than overlying sacrificial material layers, forming a retro-stepped dielectric material portion over the alternating stack in the terrace region, and forming a plurality of contact via structures through the retro-stepped dielectric material portion and on a top surface of a respective one of the electrically conductive layers within the terrace region; and
a third feature that that the ferroelectric material liners comprise an orthorhombic metal oxide of which a unit cell has a permanent non-zero electric dipole moment, and the orthorhombic metal oxide comprises an orthorhombic hafnium doped zirconium oxide or an orthorhombic hafnium oxide doped with a dopant having an atomic radius that is between 40% smaller than to 15% larger than the atomic radium of hafnium.

11. The method of claim 10 , wherein:
the substrate comprises a semiconductor material layer therein or thereon;
each of the vertical semiconductor channels is formed directly on the semiconductor material layer; and
the method further comprises:
forming a source region in, or on, the semiconductor material layer at a location that is laterally offset from the vertical semiconductor channels; and
forming drain regions at an upper end of each of the vertical semiconductor channels.

12. The method of claim 10 , wherein the method comprises the first feature.

13. The method of claim 12 , wherein the combined spac

Assignees

• Sandisk Technologies Llc

Inventors

• Chen Yangyin
• Petti Christopher

Classifications

• G11C11/2257 Primary

  Word-line or row circuits · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• H01L27/11597 Primary

  Electricity · mapped topic

• H01L27/1159

  Electricity · mapped topic

• G11C11/2273

  Reading or sensing circuits or methods · CPC title