Systems and methods for manufacturing microelectronic devices

Patent metadata

Field	Value
Publication number	US-11244873-B2
Application number	US-201916666087-A
Country	US
Kind code	B2
Filing date	Oct 28, 2019
Priority date	Oct 31, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function.

First claim

What is claimed is:

1. A method comprising:
obtaining wafer measurements of a characteristic of a semiconductor wafer at a plurality of process steps during a semiconductor wafer fabrication process, wherein at least one of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained;
creating a process step fingerprint from the obtained wafer measurements for each process step; and
correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function, the transfer function mapping the process step fingerprint of one of the plurality of process steps with the process step fingerprint of another one of the plurality of process steps.

2. The method of claim 1 , wherein obtaining the wafer measurements comprises making the wafer measurements.

3. The method of claim 1 , wherein creating the process step fingerprint comprises fitting a fingerprint model to the obtained wafer measurements for at least one of the plurality of process steps.

4. The method of claim 1 , further comprising:
for each of the plurality of process steps, associating a process parameter from a plurality of process parameters, wherein at least one of the plurality of process parameters is associated with an adjustable condition of the fabrication process.

5. The method of claim 4 , further comprising:
based on the transfer function, associating predictable characteristics of the process step fingerprint produced by the fabrication process with a particular process parameters for one of the process steps.

6. The method of claim 5 , further comprising adjusting the particular process parameters to produce semiconductor wafers having associated predictable characteristics.

7. The method of claim 1 , wherein the transfer function is a function that correlates to the process step fingerprints from a set of derived coefficients.

8. The method of claim 7 , wherein the function includes one or more orthogonal functions selected from a Zernike polynomial, a Legendre polynomial, a Fourier series, and a Bessel function.

9. The method of claim 7 , further comprising, based on the transfer function, associating coefficients of the function with a particular process parameter.

10. The method of claim 7 , further comprising:
based on the transfer function, partitioning the process step fingerprint into two component vectors:
an immediate step vector that correlates a most recent one of the plurality of process steps; and
a transferred vector that is predictable from a processing history prior to the most recent one of the plurality of process steps.

11. A method comprising:
having a fabrication process for manufacturing a plurality of semiconductor wafers, the fabrication process comprising a plurality of process steps, at least one of the plurality of process steps being associated with a set of process parameters;
performing a first process step from the plurality of process steps on a first semiconductor wafer, the first process step having an associated first process parameter, the first process parameter having a first process parameter value when performing the first process step on the first semiconductor wafer;
obtaining first measurements from the first semiconductor wafer, the first measurements comprising first characteristic values of a first characteristic at a first plurality of spatial locations on the first semiconductor wafer;
generating a first process step fingerprint for the first process step from the first measurements;
performing the first process step and a second process step from the plurality of process steps on a second semiconductor wafer, the second process step having an associated second process parameter, the second process parameter having a second process parameter value when performing the second process step on the second semiconductor wafer;
obtaining second measurements from the second semiconductor wafer, the second measurements comprising second characteristic values of a second characteristic at a second plurality of spatial locations on the second semiconductor wafer;
generating a second process step fingerprint for the second process step from the second measurements; and
correlating the first process step fingerprint to the second process step fingerprint to produce a transfer function between the first process step and the second process step.

12. The method of claim 11 , further comprising:
performing the first process step and the second process step on a plurality of third semiconductor wafers, the first process parameter having the first process parameter value and the second process parameter having a plurality of second process parameter values when performing the first process step and the second process step on the plurality of third semiconductor wafers;
obtaining a plurality of third measurements from the plurality of third semiconductor wafers, the plurality of third measurements comprising third characteristic values of the second characteristic at the second plurality of spatial locations on the plurality of third semiconductor wafers; and
generating a plurality of second process step fingerprints for the second process step from the third measurements; and
generating a process model for the second process step based on the plurality of second process step fingerprints and the transfer function, the process model comprising a function of a second process parameter.

13. The method of claim 12 , further comprising:
generating a process model for at least one of the plurality of process steps.

14. The method of claim 13 , further comprising:
modifying a value for the second process parameter at the second process step; and fabricating a semiconductor wafer with the modified value for the second process parameter.

15. The method of claim 12 , wherein at least one of the plurality of second process step fingerprints comprises a set of coefficient values associated with its respective one of the plurality of second process parameter values.

16. The method of claim 15 , wherein generating the process model comprises:
dividing at least one of the set of coefficient values into an independent component value and a transferred component value by using the transfer function; and
fitting the independent component value for at least one of the set of coefficient values with the plurality of second process parameter values to obtain the process model.

17. The method of claim 11 , further comprising:
generating a process model for the first process step by generating a reduced first process step fingerprint.

18. The method of claim 11 , wherein the transfer function comprises one or more orthogonal functions selected from a Zernike polynomial, a Legendre polynomial, a Fourier polynomial, and a Bessel function.

19. A non-transitory computer-readable storage medium comprising instructions that when executed cause a processor of a computing device to perform operations in coordination with a semiconductor wafer fabrication process, the semiconductor wafer fabrication process comprising a plurality of process steps, at least one of the plurality of process steps being associated with a set of process parameters, the operations comprising:
performing a first process step from a plurality of process steps on a first semiconductor wafer, the first process step having an associated first process parameter, the first process paramet

Assignees

• Tokyo Electron Ltd

Inventors

• Fonseca Carlos A
• Ip Nathan

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G06V40/12

  Fingerprints or palmprints · CPC title

• B81C1/00261

  Processes for packaging MEMS devices (MEMS packages B81B7/0032, packaging of smart-MEMS B81C1/0023) · CPC title

• H01L22/12 Primary

  Electricity · mapped topic