Method for forming semiconductor device structure

Patent metadata

Field	Value
Publication number	US-11239092-B2
Application number	US-202016858820-A
Country	US
Kind code	B2
Filing date	Apr 27, 2020
Priority date	Sep 28, 2017
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, comprising:
forming a first layer over a substrate, wherein the first layer is made of a semiconductor material;
forming a stop layer over the first layer;
forming a second layer over the stop layer, wherein the second layer is in direct contact with the stop layer;
partially removing the second layer;
performing an etching process to partially remove the stop layer and an upper portion of the first layer; and
performing a first planarization process of the first layer.

2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the removing of the second layer comprises:
performing a second planarization process until the stop layer is exposed.

3. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the first planarization process uses a first polishing solution, the second planarization process uses a second polishing solution, and a first abrasive material concentration of the first polishing solution is less than a second abrasive material concentration of the second polishing solution.

4. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the second planarization process uses a polishing solution, and a portion of the polishing solution remains on or in the stop layer and forms residues after the second planarization process.

5. The method for forming the semiconductor device structure as claimed in claim 4 , whereby protrusion structures are formed on a lower portion of the first layer as a result of the etching process.

6. The method for forming the semiconductor device structure as claimed in claim 5 , wherein the residues, the stop layer under the residues, and the upper portion of the first layer under the residues together form the protrusion structures, and the first planarization process removes the protrusion structures.

7. The method for forming the semiconductor device structure as claimed in claim 2 , wherein the first planarization process comprises a first chemical mechanical polishing process, and the second planarization process comprises a second chemical mechanical polishing process, the first planarization process uses a first polishing pad to polish the first layer, the second planarization process uses a second polishing pad to polish the second layer, and the first polishing pad is softer than the second polishing pad.

8. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the first layer and the second layer are made of a same material, and the stop layer and the second layer are made of different materials.

9. A method for forming a semiconductor device structure, comprising:
providing a first layer;
forming a second layer over the first layer, wherein the second layer is made of a semiconductor material;
performing a first planarization process to remove an upper portion of the second layer;
performing a first cleaning process;
performing an etching process to partially remove an upper portion of the first layer; and
performing a second planarization process of the first layer.

10. The method for forming the semiconductor device structure as claimed in claim 9 , wherein the first planarization process uses a polishing solution comprising an abrasive material, a portion of the abrasive material remains on the first layer and forms residues after the first planarization process, and the first cleaning process removes the residues.

11. The method for forming the semiconductor device structure as claimed in claim 9 , wherein the first cleaning process uses a first cleaning solution comprising a first chelating agent, the first cleaning solution is an acid solution, and the first chelating agent comprises citric acid, oxalic ligand acid, ethylenediamine tetraacetic acid, or etidronic acid.

12. The method for forming the semiconductor device structure as claimed in claim 11 , wherein the first cleaning process uses a brush, the brush is soaked in a second cleaning solution before the first cleaning process, and the second cleaning solution comprises a second chelating agent.

13. The method for forming the semiconductor device structure as claimed in claim 12 , wherein the second chelating agent comprises citric acid, oxalic ligand acid, ethylenediamine tetraacetic acid, or etidronic acid.

14. The method for forming the semiconductor device structure as claimed in claim 9 , further comprising:
after the first planarization process and before the first cleaning process, performing a second cleaning process, wherein the second cleaning process uses a cleaning solution, and the cleaning solution is an alkaline solution.

15. The method for forming the semiconductor device structure as claimed in claim 9 , wherein the etching process further removes the second layer remaining over the first layer after the first planarization process.

16. A method for forming a semiconductor device structure, comprising:
forming a first layer over a substrate, wherein the substrate comprises a base portion and a fin portion over the base portion, and the first layer covers the fin portion and the base portion;
forming a second layer over the first layer;
performing a planarization process to remove a portion of the second layer;
performing an etching process to remove an upper portion of the first layer, whereby protrusion structures are formed over a lower portion of the first layer by the etching process; and
removing the protrusion structures.

17. The method for forming the semiconductor device structure as claimed in claim 16 , wherein the planarization process uses a polishing solution, and the protrusion structures are composed of residues coming from the polishing solution and the upper portion of the first layer under the residues.

18. The method for forming the semiconductor device structure as claimed in claim 17 , further comprising:
after performing the planarization process and before performing the etching process, performing a first cleaning process, wherein the first cleaning process uses a first cleaning solution comprising a chelating agent.

19. The method for forming the semiconductor device structure as claimed in claim 18 , further comprising:
after performing the planarization process and before performing the first cleaning process, performing a second cleaning process, wherein the second cleaning process uses a second cleaning solution, and the second cleaning solution is an alkaline solution.

20. The method for forming the semiconductor device structure as claimed in claim 16 , further comprising:
after removing the protrusion structures, forming a mask layer over the first layer, wherein a portion of the first layer is not covered by the mask layer; and
removing the portion of the first layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wei Yu-Chen
• Chan Chun-Chieh
• Chu Chun-Jui
• Lai Jen-Chieh
• Lin Shih-Ho

Classifications

• H10P72/0414

  using mainly spraying means, e.g. nozzles · CPC title

• H10P72/0412

  using mainly scrubbing means, e.g. brushes · CPC title

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title