Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11233122-B2
Application number	US-202016943103-A
Country	US
Kind code	B2
Filing date	Jul 30, 2020
Priority date	Jan 14, 2020
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending lengthwise in a first direction parallel to an upper surface of the substrate;
a gate structure on the active pattern, the gate structure extending lengthwise in a second direction parallel to the upper surface of the substrate and crossing the first direction;
channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending lengthwise through the gate structure along the first direction;
a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels;
inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and
channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other.

2. The semiconductor device as claimed in claim 1 , wherein each of the inner spacers has a shape protruding inwardly toward a center of the gate structure in the first direction.

3. The semiconductor device as claimed in claim 2 , wherein each of the channel connection portions covers an inner sidewall, an upper surface, and a lower surface of a corresponding one of the inner spacers.

4. The semiconductor device as claimed in claim 3 , wherein each of the channel connection portions directly contacts the source/drain layer.

5. The semiconductor device as claimed in claim 1 , wherein the gate structure includes an interface pattern, a gate insulating pattern, a work function control pattern, and a gate electrode sequentially stacked from an surface of each of the channels, an upper surface of the active pattern, and an inner sidewall of the channel connection portion.

6. The semiconductor device as claimed in claim 5 , wherein:
the interface pattern includes silicon oxide, and
the gate insulating pattern includes a metal oxide.

7. The semiconductor device as claimed in claim 5 , further comprising a gate spacer covering a sidewall of a portion of the gate structure on an uppermost one of the channels,
wherein the interface pattern is not formed on an inner sidewall of the gate spacer.

8. The semiconductor device as claimed in claim 7 , wherein each of the channels extends outwardly beyond the gate spacer toward the source/drain layer in a plan view.

9. The semiconductor device as claimed in claim 1 , wherein the channels and the channel connection portions each include single crystalline silicon.

10. The semiconductor device as claimed in claim 1 , wherein the inner spacers include silicon nitride, silicon carbonitride, silicon boronitride, or silicon oxycarbonitride.

11. The semiconductor device as claimed in claim 1 , wherein a portion of the gate structure between the channels has a thickness in the third direction greater than a thickness in the third direction of a corresponding one of the inner spacers adjacent thereto in the first direction.

12. The semiconductor device as claimed in claim 1 , wherein each of the inner spacers has a thickness in the third direction that gradually increases toward the source/drain layer in the first direction.

13. The semiconductor device as claimed in claim 1 , wherein a thickness, in the third direction, of each of the inner spacers gradually increases to a maximum thickness and then gradually decreases toward the source/drain layer in the first direction.

14. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending lengthwise in a first direction parallel to an upper surface of the substrate;
a gate structure on the active pattern, the gate structure extending lengthwise in a second direction parallel to the upper surface of the substrate and crossing the first direction;
channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending lengthwise through the gate structure along the first direction;
a source/drain layer on a portion of the active pattern portion adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; and
a channel connection portion and an inner spacer sequentially stacked along the first direction between the gate structure and the source/drain layer, the channel connection portion including a semiconductor material and the inner spacer including silicon nitride,
wherein the gate structure includes an interface pattern, a gate insulating pattern and a gate electrode sequentially stacked along the first direction from the channel connection portion, the interface pattern including silicon oxide, the gate insulating pattern including a metal oxide, and the gate electrode including a metal.

15. The semiconductor device as claimed in claim 14 , wherein the channel connection portion connects:
the channels with each other, and
a lowermost one of the channels with the active pattern.

16. The semiconductor device as claimed in claim 14 , wherein the channel connection portion includes the same semiconductor material as the channels.

17. The semiconductor device as claimed in claim 14 , wherein the inner spacer has a shape protruding inwardly toward a center of the gate structure in the first direction.

18. The semiconductor device as claimed in claim 17 , wherein the channel connection portion covers an inner sidewall, an upper surface, and a lower surface of the inner spacer.

19. The semiconductor device as claimed in claim 18 , wherein the channel connection portion directly contacts the source/drain layer.

20. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending lengthwise in a first direction parallel to an upper surface of the substrate;
channels on the active pattern, the channels being spaced apart from each other along a third direction perpendicular to the upper surface of the substrate;
a gate structure extending lengthwise on the active pattern in a second direction parallel to the upper surface of the substrate and crossing the first direction, the gate structure at least partially covering each of the channels;
source/drain layers at respective opposite sides of the gate structure in the first direction, each of the source/drain layers contacting the channels;
inner spacers between the active pattern and a lowermost one of the channels and between the channels, respectively, the inner spacers contacting the source/drain layers;
gate spacers covering respective opposite sidewalls of a portion of the gate structure on an uppermost one of the channels; and
channel connection portions between the gate structure and a corresponding one of the inner spacers, the channel connection portions connecting the active pattern and the lowermost one of the channels, and connecting the channels with each other, and the channel connection portions covering an inner sidewall, an upper surface, and a lower surface of a corresponding one of the inner spacers,
wherein the gate structure includes an interface pattern, a gate insulating pattern, a gate electrode sequentially stacked from an surface of each of the channels, an upper surface of the active pattern and an inner sidewall of the channel connection portion, the interface pattern including a silicon oxide, the gate insulating pattern including a metal oxide, a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sangsu
• Park Junbeom
• Yang Junggil

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title