Method of manufacturing a semiconductor device and a semiconductor device

Patent metadata

Field	Value
Publication number	US-2019123163-A1
Application number	US-201816198046-A
Country	US
Kind code	A1
Filing date	Nov 21, 2018
Priority date	Aug 30, 2017
Publication date	Apr 25, 2019
Grant date	—

Abstract

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
first semiconductor wires disposed over a substrate; a first source/drain region in contact with the first semiconductor wires; a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires; a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region; first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region; and air gaps disposed in the spaces, respectively.

2 . The semiconductor device of claim 1 , further comprising second insulating spacers disposed in the spaces, respectively.

3 . The semiconductor device of claim 2 , wherein the air gaps are in contact with the first source/drain region.

4 . The semiconductor device of claim 2 , wherein the second insulating spacers are made of a low-k dielectric material.

5 . The semiconductor device of claim 4 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.

6 . The semiconductor device of claim 1 , wherein each of the first insulating spacers has a V-shape cross section.

7 . The semiconductor device of claim 1 , wherein the first source/drain region and the gate electrode layer are separated by the first insulating spacers, the air gaps and a gate dielectric layer.

8 . The semiconductor device of claim 1 , wherein the first source/drain region is in contact with ends of the first semiconductor wires.

9 . The semiconductor device of claim 1 , wherein the first source/drain region wraps around parts of the first semiconductor wires.

10 . A semiconductor device, comprising:
first semiconductor wires disposed over a substrate; a first source/drain epitaxial layer wrapping around source/drain regions of the first semiconductor wires; a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires; a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region; first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region; and air gaps disposed in the spaces, respectively.

11 . The semiconductor device of claim 10 , wherein the first semiconductor wires are made of SiGe or Ge.

12 . The semiconductor device of claim 10 , further comprising second insulating spacers disposed in the spaces, respectively.

13 . The semiconductor device of claim 12 , wherein the air gaps are in contact with the first source/drain region.

14 . The semiconductor device of claim 12 , wherein the second insulating spacers are made of a low-k dielectric material.

15 . The semiconductor device of claim 14 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.

16 . The semiconductor device of claim 10 , wherein each of the first insulating spacers has a V-shape cross section.

17 . The semiconductor device of claim 10 , wherein the first source/drain region and the gate electrode layer are separated by the first insulating spacers, the air gaps and the gate dielectric layer.

18 . A semiconductor device, comprising:
first semiconductor wires disposed over a substrate; a first source/drain epitaxial layer wrapping around source/drain regions of the first semiconductor wires; a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires; a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region; first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region; and second insulating spacers disposed in the spaces, respectively.

19 . The semiconductor device of claim 18 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiO 2 and SiN.

20 . The semiconductor device of claim 19 , wherein the second insulating spacers are made of at least one selected from the group consisting of SiOC and SiOCN.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Yu-Lin
• Lee Tung Ying
• Yu Shao-Ming
• Cheng Chao-Ching
• Chen Tzu-Chiang
• Huang Chao-Hsien

Classifications

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title