Multi-chip package with reduced calibration time and ZQ calibration method thereof

Patent metadata

Field	Value
Publication number	US-11217283-B2
Application number	US-202017012845-A
Country	US
Kind code	B2
Filing date	Sep 4, 2020
Priority date	Sep 3, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

First claim

What is claimed is:

1. A multi-chip package comprising:
a printed circuit board; and
a plurality of memory chips stacked on the printed circuit board and including:
a master memory chip; and
a plurality of slave memory chips,

wherein each of the plurality of memory chips includes:
a memory cell region including a first metal pad;
a peripheral circuit region including a second metal pad and being vertically connected to the memory cell region by the first metal pad and the second metal pad;
an impedance control (ZQ) pad; and
a plurality of data input/output (DQ) pads,

wherein the master memory chip is configured to perform a first ZQ calibration operation on a ZQ pad of the master memory chip using a ZQ resistor connected to a ZQ terminal of the multi-chip package and control termination resistance values of the plurality of DQ pads of the master memory chip based on the first ZQ calibration operation, and
wherein each slave memory chip of the plurality of slave chips is configured to perform second ZQ calibration operations on DQ pads of first to m th slave memory chips of the plurality of slave memory chips based on termination resistance values of first to m th DQ pads of the plurality of DQ pads of the master memory chip based on a ZQ calibration option set between the first to m th DQ pads of the master memory chip and the DQ pads of the first to m th slave memory chips, m being an integer greater than 1.

2. The multi-chip package of claim 1 , wherein:
the master memory chip further includes a ZQ calibration circuit in the peripheral circuit region, and
the plurality of slave chips are configured to simultaneously perform the second ZQ calibration operations.

3. The multi-chip package of claim 2 , wherein the plurality of slave memory chips are configured such that a time for completing the second ZQ calibration operations performed by the plurality of slave memory chips is shorter than two times a time for completing a second ZQ calibration operation performed by one slave memory chip amongst the plurality of slave memory chips.

4. The multi-chip package of claim 1 , wherein the ZQ pad of each slave memory chip is connected to a source voltage line or a ground voltage line.

5. The multi-chip package of claim 1 , wherein the first to m th DQ pads of the master memory chip are respectively connected to first to m th pads of each of the first to m th slave memory chips.

6. The multi-chip package of claim 1 , wherein the ZQ calibration option is stored in a register of the master memory chip.

7. The multi-chip package of claim 1 , wherein the ZQ calibration option is stored in a register of each of the plurality of memory chips.

8. The multi-chip package of claim 1 , wherein:
each of the plurality of memory chips includes a ZQ engine connected to the ZQ pad, and
the ZQ engine included in each of the plurality of memory chips comprises:
a master/slave determiner circuit configured to detect a voltage level of the ZQ pad and compare the detected voltage level of the ZQ pad with a source voltage level or a ground voltage level to determine whether a corresponding memory chip is the master memory chip or one of the plurality of slave memory chips;
a first comparator configured to compare the voltage level of the ZQ pad with a reference voltage level based on the master/slave determiner circuit determining that the corresponding memory chip is the master memory chip;
a second comparator;
a multiplexer configured to provide, as a first input, an output of the first comparator in the master memory chip and provide, as a second input, an output of a third comparator of each of DQ drivers connected to the DQ pads in the plurality of slave memory chips;
a first pull-up circuitry configured to perform a pull-up calibration operation that includes generating a pull-up calibration code on the basis of an output of the multiplexer; and
a second pull-up circuitry of which an impedance is controllable to be equal to an impedance of the first pull-up circuitry on the basis of the pull-up calibration code, the second comparator being configured to compare the reference voltage level with a voltage level of a connection node between the second pull-up circuitry and first pull-down circuitry, the first pull-down circuitry being configured to perform a pull-down calibration operation of generating a pull-down calibration code based on the an output of the second comparator.

9. The multi-chip package of claim 8 , wherein the ZQ calibration option is stored in the master/slave determiner circuit.

10. The multi-chip package of claim 8 , wherein each of the DQ drivers comprises:
a third pull-up circuitry configured to control a pull-up termination resistance of each of the DQ pads based on the pull-up calibration code; and
a second pull-down circuitry configured to control a pull-down termination resistance based on the pull-down calibration code, the third comparator being configured to compare a voltage level of each of the DQ pads with the reference voltage level.

11. The multi-chip package of claim 1 , wherein the memory cell region is formed on a first wafer and the peripheral circuit region is formed on a second wafer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Junha
• Lee Seonkyoo
• Ihm Jeongdon
• Jeong Byunghoon

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title