Semiconductor apparatus and memory system

Patent metadata

Field	Value
Publication number	US-9917061-B2
Application number	US-201314014625-A
Country	US
Kind code	B2
Filing date	Aug 30, 2013
Priority date	May 20, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

First claim

What is claimed is:

1. A semiconductor apparatus comprising:
a stacked chip comprising multiple chips;
a non-first chip of the multiple chips further comprising:
a chip ID generation unit configured to generate a chip ID signal;
a chip ID transmission unit configured to output the chip ID signal to a common line when a next chip does not exist in the stacked chip; and
a chip stack information generation unit configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal,
wherein a first chip of the multiple chips is configured to directly receive the chip ID signal of the non-first chip when the next chip does not exist in the stacked chip, and
wherein the chip ID transmission unit comprises:
a determining section configured to generate a transmission enable signal on the basis of whether an output terminal thereof is electrically coupled with the the another stacked chip at the next stage; and
a transmitting section configured to transmit the chip ID signal to the common line in response to the transmission enable signal.

2. The semiconductor apparatus according to claim 1 , wherein the determining section disables the transmission enable signal in the case where the output terminal thereof is electrically coupled with the another stacked chip and enables the transmission enable signal in the case where the output terminal thereof is floated.

3. The semiconductor apparatus according to claim 2 , wherein the determining section comprises:
a transistor configured to generate a signal with a first voltage level in response to a control signal; and
an inverter configured to receive the signal with the first voltage level and provide a signal with a second voltage level as the transmission enable signal.

4. The semiconductor apparatus according to claim 1 , wherein the chip stack information generation unit generates the stack information signal from the chip ID signal which is transmitted through the common line, in response to a reception enable signal which is generated on the basis of the chip ID signal.

5. The semiconductor apparatus according to claim 4 , wherein the chip stack information generation unit comprises:
a decoding section configured to decode the chip ID signal and generate the reception enable signal.

6. The semiconductor apparatus according to claim 4 , wherein the chip stack information generation unit comprises:
a receiving section configured to receive the chip ID signal transmitted through the common line in response to the reception enable signal and generate the stack information signal.

7. A semiconductor apparatus having sequentially stacked therein three or more chips which include a first chip stacked at a first stage and an other chip stacked at a last stage,
wherein each of the three or more chips include chip ID generation units, which are respectively disposed in the three or more chips, are sequentially electrically coupled with one another and generate a plurality of chip ID signals, and
wherein the first chip is configured to directly receive the chip ID signal of the other chip and generate a stack information signal from the chip ID signal of the other chip,
wherein the semiconductor apparatus further includes a common line which is electrically coupled in common with the three or more chips,
wherein each of the three or more chips comprises a chip ID transmission unit which is configured to transmit the chip ID signal of the corresponding chip at a current stage to the common line on the basis of whether a stacked chip exists at a next stage, and
wherein the chip ID transmission unit comprises:
a determining section configured to generate a transmission enable signal on the basis of whether an output terminal thereof is electrically coupled with another chip; and
a transmitting section configured to transmit the chip ID signal of the chip in which it is disposed, to the common line in response to the transmission enable signal.

8. The semiconductor apparatus according to claim 7 , wherein the chip ID transmission unit of the other chip transmits the chip ID signal of the other chip to the common line, and the chip ID transmission units of the remaining chips excluding the other chip block the chip ID signals of the chips in which they are disposed, from being outputted to the common line.

9. The semiconductor apparatus according to claim 7 , wherein each of the three or more chips comprises a chip stack information generation unit which is configured to be electrically coupled with the common line and generate a stack information signal from the chip ID signal transmitted through the common line, when it is enabled in response to the chip ID signal of the chip in which it is disposed.

10. The semiconductor apparatus according to claim 9 , wherein the chip stack information generation unit comprises:
a decoding section configured to decode the chip ID signal of the chip in which it is disposed, and generate a reception enable signal; and
a receiving section configured to receive the chip ID signal transmitted through the common line in response to the reception enable signal and generate the stack information signal.

11. The semiconductor apparatus according to claim 9 , wherein the first chip receives the chip ID signal of the other chip which is transmitted through the common line and generates the stack information signal, and the remaining chips of the three or more chips, excluding the first chip, do not generate a stack information signal.

Assignees

• Sk Hynix Inc

Inventors

• Byeon Sang Jin

Classifications

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W46/601

  for use after dicing · CPC title

• H10W46/403

  for non-wireless electrical read out · CPC title