ZQ calibration method of memory device with shared ZQ pin and memory device performing the ZQ calibration method

Patent metadata

Field	Value
Publication number	US-10276220-B2
Application number	US-201715674250-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Dec 1, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first die may be configured to perform a first calibration operation using the resistor in response to a ZQ calibration command applied from outside of the memory device. The first die may be configured to generate a ZQ flag signal after the first calibration operation ends and perform a second calibration operation. The second die may be configured to perform the first calibration operation in response to the ZQ flag signal and perform a second calibration after the first calibration operation of the second die ends.

First claim

What is claimed is:

1. An output impedance control (ZQ) calibration method performed by a memory device comprising a first die and a second die that share a resistor connected to a ZQ pin, the ZQ calibration method comprising:
performing a first calibration operation for the first die using the resistor in response to a ZQ calibration command applied from outside of the memory device;
after the first calibration operation of the first die ends, generating a ZQ flag signal from the first die and performing a second calibration operation of the first die;
performing a first calibration operation of the second die using the resistor in response to the ZQ flag signal; and
after the first calibration operation of the second die ends, performing a second calibration of the second die,
wherein the first calibration operation of each of the first and second dies is one of a pull-up calibration operation which generates a pull-up calibration code and a pull-down calibration operation which generates a pull-down calibration code, used to adjust a termination resistance value of each of the first and second dies, and
wherein the second calibration operation of each of the first and second dies is the other one of the pull-up calibration operation and the pull-down calibration operation.

2. The ZQ calibration method of claim 1 , wherein the second calibration operation of the first die and the first calibration operation of the second die overlap during a period of time.

3. The ZQ calibration method of claim 1 , wherein the second calibration operation of the first die starts before the first calibration operation of the second die starts.

4. The ZQ calibration method of claim 1 , further comprising:
transmitting the ZQ flag signal to the second die through a wired interconnection between the first die and the second die.

5. The ZQ calibration method of claim 1 , further comprising:
packaging the resistor with the first die and the second die into the memory device.

6. A memory device comprising:
a resistor;
a first die comprising a first pad connected to the resistor, the first die configured to perform a first calibration operation using the resistor in response to an output impedance control (ZQ) calibration command, generate a ZQ flag signal when the first calibration operation is performed, and additionally perform a second calibration operation of the first die; and
a second die comprising a second pad connected to the resistor, the second die configured to perform a first calibration operation using the resistor in response to the ZQ flag signal, and additionally perform a second calibration operation of the second die,
wherein each of the first and second dies comprises an output driver,
wherein the output driver comprises a pull-up driver and a pull-down driver,
wherein the first calibration operation of each of the first and second dies is one of a pull-up calibration operation that provides a pull-up calibration code to the pull-up driver of each of the first and second dies and a pull-down calibration operation that provides a pull-down calibration code to the pull-down driver of each of the first and second dies, used to adjust a termination resistor of the output driver of each of the first and second dies, and
wherein the second calibration operation of each of the first and second dies is the other one of the pull-up calibration operation and the pull-down calibration operation.

7. The memory device of claim 6 , wherein the resistor, the first die, and the second die are packaged into the memory device.

8. The memory device of claim 6 , further comprising:
a wired interconnection connected between a third pad of the first die and a fourth pad of the second die,
wherein the third pad is configured to output the ZQ flag signal, and
wherein the fourth pad is configured to receive the ZQ flag signal.

9. The memory device of claim 6 , further comprising:
a first channel and a second channel each channel comprising signal lines transmitting a command, an address, and data to the first die and the second die, respectively,
wherein the ZQ calibration command is provided through the first channel.

10. The memory device of claim 6 , wherein the first die is configured to transmit the ZQ flag signal to the second die through a signal line connected between a pad of the first die and a pad of the second die.

11. The memory device of claim 6 , wherein the first die is configured to perform the second calibration operation and the second die is configured to perform the first calibration operation overlapping with the second calibration operation of the first die during a period of time.

12. The memory device of claim 11 , wherein the first die is configured to perform the second calibration operation before the first calibration operation of the second die starts.

13. An electronic device comprising:
a first memory device comprising a first output driver connected to a resistor, and configured to perform a calibration operation using the resistor; and
a second memory device comprising a second output driver connected to the resistor, and configured to perform a calibration operation using the resistor during the calibration operation of the first memory device,
wherein the first memory device is configured to adjust a resistance value of the first output driver during the calibration operation of the first memory device,
wherein the second memory device is configured to adjust a resistance value of the second output driver during the calibration operation of the second memory device,
wherein the first output driver includes a first pull-up driver and a first pull-down driver and the second output driver includes a second pull-up driver and a second pull-down driver,
wherein the first memory device is configured to provide a first calibration code to one of the first pull-up driver and the first pull-down driver of the first output driver during a first calibration operation of the first memory device, and provide a second calibration code to the other one of the first pull-up driver and the first pull-down driver of the first output driver during a second calibration operation of the first memory device later the first calibration operation,
wherein the second memory device is configured to provide a third calibration code to one of the second pull-up driver and the second pull-down driver of the second output driver during a third calibration operation of the second memory device, and provide a fourth calibration code to the other one of the second pull-up driver and the second pull-down driver of the second output driver during a fourth calibration operation of the second memory device later the third calibration operation, and
wherein the second calibration operation and the third calibration operation overlap during a period of time.

14. The electronic device of claim 13 , wherein the first memory device is configured to perform the second calibration operation before the third calibration operation of the second memory device starts.

15. The electronic device of claim 13 , wherein the first memory device is configured to end the second calibration operation before the fourth calibration operation of the second memory device ends.

16. The electronic device of claim 13 , wherein the first memory device is configured to perform the first calibration operation in response to an output impedance control (ZQ) calibration command applied from an external device, and generate a ZQ flag signal when the first calibration operation ends, and
wherein the second memory device is co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Juho
• Choi Hun-Dae

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C29/025

  in signal lines · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H01L25/0657

  Electricity · mapped topic

• G11C29/028

  with adaption or trimming of parameters · CPC title