Semiconductor device having interconnection in package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9805769-B2
Application number	US-201514697634-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Jul 9, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first die connected to a first channel, the first die comprising a first memory chip; and
a second die connected to a second channel, the second die comprising a second memory chip at the same vertical level as the first memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die,
wherein the first and second dies are disposed in one package;
wherein the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip, wherein:
the first channel is a channel dedicated to the first memory chip for receiving a first type of signal from outside the semiconductor device;
the second channel is a channel dedicated to the second memory chip for receiving the first type of signal from outside the semiconductor device; and
the interconnection circuit comprises a common channel shared by the first and second memory chips for receiving a second type of signal different from the first type of signal from the outside of the package at only one of the first and second memory chips from among the first and second memory chips, and applying the second type of signal to both the first memory chip and the second memory chip.

2. The semiconductor device of claim 1 , wherein:
the first type of signal is an address, data, or command signal; and
the second type of signal is an operational control signal that includes one of an impedance calibration signal and a reset signal.

3. A semiconductor device comprising:
a first die connected to a first channel, the first die comprising a first memory chip; and
a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die,
wherein the first and second dies are disposed in one package;
wherein the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip;
wherein the first and second dies are positioned to have side edges that are aligned with each other;
wherein the first and second dies are disposed in the package and are arranged in a rotated die configuration; and
wherein the first die includes a first swapping circuit configured to change a signal order of signals received at die pads of the first die in response to a swapping enable signal.

4. The semiconductor device of claim 3 , wherein the second die includes a second swapping circuit configured to change a signal order of signals received at die pads of the second die in response to the swapping enable signal.

5. The semiconductor device of claim 4 , wherein the second swapping circuit is enabled in response to the swapping enable signal when the first swapping circuit is disabled.

6. A semiconductor device, comprising:
a package substrate;
a first semiconductor memory chip on the substrate;
a second semiconductor memory chip on the substrate and horizontally separated from the first semiconductor memory chip so that a space is formed between a first edge of the first semiconductor memory chip and a first edge of the second semiconductor chip;
a first set of pads on the first semiconductor chip connected to a first channel dedicated to the first semiconductor chip;
a second set of pads on the second semiconductor chip connected to a second channel dedicated to the second semiconductor chip;
a third set of pads on the first semiconductor chip connected to an interconnection circuit on the package substrate; and
a fourth set of pads on the second semiconductor chip connected to the interconnection circuit,
wherein the interconnection circuit transfers certain signals received from and processed at the first semiconductor chip to the second semiconductor chip, such that the second semiconductor chip receives the processed signals from the first semiconductor chip.

7. The semiconductor device of claim 6 , wherein:
the first semiconductor chip receives a first type of signal over the first channel;
the second semiconductor chip receives the first type of signal over the second channel; and
the certain signals transferred by the interconnection circuit are second type of signal different from the first type of signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaehyung
• Kim Jungsik
• Lee Youngdae
• Kim Duyeul
• Yim Sungmin
• Park Kwangil
• Park Chulsung

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title