FinFET devices including recessed source/drain regions having optimized depths
US-10147793-B2 · Dec 4, 2018 · US
US11201250B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11201250-B2 |
| Application number | US-202016848826-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 14, 2020 |
| Priority date | Apr 16, 2019 |
| Publication date | Dec 14, 2021 |
| Grant date | Dec 14, 2021 |
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A Schottky barrier diode includes a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer, and a metal layer formed on the second semiconductor layer to form a Schottky barrier, wherein the first semiconductor layer and the second semiconductor layer are formed of different materials, and a conduction band offset between the first semiconductor layer and the second semiconductor layer is less than a set value.
Opening claim text (preview).
What is claimed is: 1. A Schottky barrier diode comprising: a substrate; a first semiconductor layer formed on the substrate; a buffer layer formed between the substrate and the first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; and a Schottky metal layer formed on the second semiconductor layer to form a Schottky barrier, wherein the buffer layer is formed from a same material as the first semiconductor layer, and wherein the first semiconductor layer and the second semiconductor layer are formed of different materials, and a conduction band offset between the first semiconductor layer and the second semiconductor layer is less than a set value. 2. The Schottky barrier diode of claim 1 , wherein the first semiconductor layer is an n + type, and the second semiconductor layer is an n − type. 3. The Schottky barrier diode of claim 1 , wherein the set value is thermal energy at room temperature (300K). 4. The Schottky barrier diode of claim 1 , further comprising an insulating layer formed between the metal layer and the second semiconductor layer. 5. The Schottky barrier diode of claim 4 , further comprising an ohmic metal layer formed on the first semiconductor layer after etching to the second semiconductor layer and the insulating layer at a portion thereof. 6. The Schottky barrier diode of claim 1 , wherein the second semiconductor layer and the first semiconductor layer are partially etched under the Schottky metal layer. 7. A manufacturing method of a Schottky barrier diode, the manufacturing method comprising: doping a first material on a substrate to form a first semiconductor layer; doping a second material different from the first material on the first semiconductor layer to form a second semiconductor layer; forming a Schottky metal layer on the second semiconductor layer such that a Schottky barrier is formed; forming an insulating layer between the second semiconductor layer and the Schottky metal layer; and partially etching the second semiconductor layer and the first semiconductor layer under the Schottky metal layer after forming the Schottky metal layer, wherein a conduction band offset between the first semiconductor layer and the second semiconductor layer is less than a conduction band offset between a first semiconductor layer and a second semiconductor layer of same materials. 8. The manufacturing method of claim 7 , wherein the first semiconductor layer is an n + type, and the second semiconductor layer is an n − type. 9. The manufacturing method of claim 7 , further comprising forming an ohmic metal layer on the first semiconductor layer after etching to the second semiconductor layer and the insulating layer at a portion before forming the Schottky metal layer.
of Group III-V materials · CPC title
to Group III-V semiconductors · CPC title
of Schottky diodes · CPC title
comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title
Electrodes comprising a Schottky barrier to a semiconductor · CPC title
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