Device contact structures including heterojunctions for low contact resistance

Patent metadata

Field	Value
Publication number	US-9917158-B2
Application number	US-201514942193-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Jul 30, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.

First claim

What is claimed:

1. A semiconductor device comprising:
a channel region comprising a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device;
a metal contact;
a source/drain region comprising a semiconductor material alloy including a second semiconductor material; and
at least one heterojunction located in the source/drain region between the metal contact and the channel region, wherein the at least one heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV,
wherein the semiconductor material alloy comprises a graded composition of the second semiconductor material,
wherein the graded composition comprises a lean second semiconductor material concentration at an interface with the first semiconductor material of the channel region and progresses to a rich second semiconductor material concentration remote from the interface with the first semiconductor material,
wherein the graded composition comprises a graded composition of the second semiconductor material and a third semiconductor material, wherein the second semiconductor material is not fully miscible with the first semiconductor material, and
wherein the graded composition of the semiconductor material alloy comprises a rich concentration of the third semiconductor material and the lean second semiconductor material concentration at the interface with the first semiconductor material of the channel region and progresses to a lean concentration of the third semiconductor material and the rich second semiconductor material concentration at an interface with the metal contact.

2. The semiconductor device of claim 1 wherein a region of the at least one heterojunction is doped with a dopant type corresponding to conduction with the majority carrier.

3. The semiconductor of claim 1 wherein the graded composition of the semiconductor material alloy is provided by S 3 x S 2 1-x where S 3 is the third semiconductor material, S 2 is the second semiconductor material, and x=0 at the interface with the metal contact and x=1 at the interface with the first semiconductor material.

4. The semiconductor device of claim 3 wherein an increment in the graded composition of the semiconductor material alloy is configured to prevent a band-offset between contiguous grades in the graded composition being greater than about 0.2 eV.

5. The semiconductor device of claim 1 wherein the source/drain region comprises one of the third semiconductor material or the semiconductor material alloy at the interface with the metal contact and wherein respective materials of the metal contact and the one of the third semiconductor material or the semiconductor material alloy at the interface with the metal contact are selected to provide a Schottky barrier height therebetween that is equal to about 0.2 eV or less.

6. The semiconductor device of claim 1 wherein the graded composition is a linear graded composition, a non-linear graded composition, a stepped graded composition, or a combination thereof.

7. The semiconductor device of claim 1 wherein the first semiconductor material comprises at least one group IV semiconductor element, the second semiconductor material comprises a group III-V semiconductor compound or a group III-V semiconductor alloy, and the semiconductor material alloy comprises the third semiconductor material and the second semiconductor material.

8. The semiconductor device of claim 1 wherein the device comprises an NMOS device and the first semiconductor material comprises Si, a SiGe alloy, or Ge, the second semiconductor material comprises InAs, InN, an In—As—N alloy, an In—Al—As alloy, or an In—Ga—As alloy, and the third semiconductor material comprises GaAs, In—Ga—N, an In—Ga—As—N alloy, an In—Al—Ga—As alloy, or an Al—Ga—As alloy.

9. A semiconductor device comprising:
a channel region comprising a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device;
a metal contact;
a source/drain region comprising a semiconductor material alloy including a second semiconductor material; and
at least one heterojunction located in the source/drain region between the metal contact and the channel region, wherein the at least one heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV,
wherein the semiconductor material alloy comprises a graded composition of the second semiconductor material,
wherein the graded composition comprises a lean second semiconductor material concentration at an interface with the first semiconductor material of the channel region and progresses to a rich second semiconductor material concentration remote from the interface,
wherein the graded composition comprises a graded composition of the first semiconductor material and the second semiconductor material,
wherein the graded composition of the semiconductor material alloy comprises a rich concentration of the first semiconductor material and the lean second semiconductor material concentration at the interface with the first semiconductor material of the channel region and progresses to a lean concentration of the first semiconductor material and the rich second semiconductor material concentration remote from the interface to form the at least one heterojunction with a third semiconductor material, and
wherein the third semiconductor material is not fully miscible with the first semiconductor material.

10. A semiconductor device comprising:
a channel region comprising a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device;
a metal contact;
a source/drain region comprising a semiconductor material alloy including a second semiconductor material; and

at least one heterojunction located in the source/drain region between the metal contact and the channel region, wherein the at least one heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV,
wherein the semiconductor material alloy comprises a graded composition of the second semiconductor material,
wherein the graded composition comprises a lean second semiconductor material concentration at an interface with a first semiconductor material of the channel region and progresses to a rich second semiconductor material concentration remote from the interface,
wherein the graded composition comprises a graded composition of the second semiconductor material and a third semiconductor material, wherein the second semiconductor material is not fully miscible with the first semiconductor material, and
wherein the graded composition is a first graded composition of the second semiconductor material and a third semiconductor material and the semiconductor material alloy is a first graded semiconductor material alloy, the semiconductor further comprising:
a second graded composition alloy located in the source/drain region between the channel region and the first graded composition, the second graded composition alloy comprising a second graded composition of a fourth semiconductor material and a fifth semiconductor material, wherein the fifth semiconductor material is not fully miscible with the first semiconductor material.

11. An electronic device comprising:
a channel region comprising a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device;
a metal contact; and
a source/drain region comprising a material alloy including at least one semiconductor material component and is free of all components of the first semi

Assignees

• Kittl Jorge A
• Obradovic Borna Josip
• Bowen Robert Christopher
• Rodder Mark S
• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Obradovic Borna Josip
• Bowen Robert Christopher
• Rodder Mark S

Classifications

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L29/267 Primary

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic