Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration

Patent metadata

Field	Value
Publication number	US-11189639-B2
Application number	US-202016842867-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	Apr 5, 2017
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first conductive pattern in a conductive layer, the first conductive pattern comprising:
a first segment extending in a first direction,
a second segment extending in the first direction, and
a third segment extending in a second direction to connect the first segment and the second segment;

a second conductive pattern in the conductive layer between the first segment and the second segment;
at least one gate line extending in the second direction; and
at least one gate contact electrically connected to the at least one gate line,
wherein a width of the third segment is greater than both a width of the first segment and a width of the second segment,
wherein the first conductive pattern is an output pin of a standard cell, and
wherein the second conductive pattern is an input pin of the standard cell.

2. The integrated circuit of claim 1 , further comprising:
a plurality of first fins extending in the first direction on a first active region;
at least one first active contact electrically connected to the plurality of the first fins;
a plurality of second fins extending in the first direction on a second active region; and
at least one second active contact electrically connected to the plurality of the second fins.

3. The integrated circuit of claim 2 , further comprising:
at least one first via between the at least one first active contact and a bottom of the first segment;
at least one second via between the at least one second active contact and a bottom of the second segment; and
at least one third via on a top of the third segment.

4. The integrated circuit of claim 3 ,
wherein the first segment is electrically connected only to the at least one first via and the third segment, and
wherein the second segment is electrically connected only to the at least one second via and the third segment.

5. The integrated circuit of claim 1 ,
wherein the standard cell is an inverter.

6. The integrated circuit of claim 1 , further comprising:
a third conductive pattern in the conductive layer; and
a fourth conductive pattern in the conductive layer,
wherein the third conductive pattern extends in the first direction and is configured to receive a power supply voltage, and
wherein the fourth conductive pattern extends in the first direction and is configured to receive a ground voltage.

7. The integrated circuit of claim 1 ,
wherein the first segment extends in the first direction between two ends,
wherein the second segment extends in the first direction between two ends, and
wherein the third segment is connected to one of the two ends of the first segment and one of the two ends of the second segment.

8. The integrated circuit of claim 1 ,
wherein the first segment extends in the first direction between two ends,
wherein the second segment extends in the first direction between two ends, and
wherein the third segment is connected to the first segment between the two ends of the first segment and to the second segment between the two ends of the second segment.

9. The integrated circuit of claim 1 ,
wherein a distance between the third segment and one end of the first segment is different from a distance between the third segment and the other end of the first segment, and
wherein a distance between the third segment and one end of the second segment is different from a distance between the third segment and the other end of the second segment.

10. The integrated circuit of claim 1 ,
wherein the first segment has a stair shape of which the width of the first segment decreases away from the third segment in the first direction.

11. The integrated circuit of claim 10 ,
wherein the first segment has the stair shape at a first side facing the second segment and a flat shape at a second side opposite to the first side.

12. The integrated circuit of claim 10 ,
wherein the first segment has the stair shape at each of two sides facing in the second direction.

13. The integrated circuit of claim 10 ,
wherein the second segment has a stair shape of which the width of the second segment decreases away from the third segment in the first direction.

14. The integrated circuit of claim 10 ,
wherein the second conductive pattern is near a portion of the first segment having shorter width.

15. The integrated circuit of claim 14 ,
wherein the second segment has a stair shape of which the width of the second segment decreases away from the third segment.

16. An integrated circuit comprising:
a standard cell, the standard cell comprising:
a plurality of first fins extending in a first direction on a first active region,
a plurality of second fins extending in the first direction on a second active region,
a first pattern configured to receive a power supply voltage in a conductive layer,
a second pattern configured to receive a ground voltage in the conductive layer, and
an output pin disposed between the first pattern and the second pattern in the conductive layer,

wherein the output pin comprises:
a first segment and a second segment extending in the first direction to be parallel each other, and
a third segment extending in a second direction and connecting the first segment and the second segment,

wherein at least one of the first segment and the second segment has a shape of which a width decreases away from the third segment in the first direction.

17. The integrated circuit of claim 16 ,
wherein the standard cell further comprises an input pin in the conductive layer, and
wherein the input pin is disposed near a portion having a decreased width of the first segment and/or a portion having a decreased width of the second segment.

18. The integrated circuit of claim 17 ,
wherein the input pin has a shape of which a width increases away from the third segment in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Kim Chang-Beom
• Roh Hyun-Jeong
• Song Tae-Joong
• Lee Dal-Hee
• Cho Sung-We

Classifications

• H10D84/985

  Two levels of metal · CPC title

• H10D84/981

  Power supply lines · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/964

  Yield or reliability · CPC title

• H10D84/961

  Substrate and well contacts · CPC title