Via placement within an integrated circuit

Patent metadata

Field	Value
Publication number	US-9454633-B2
Application number	US-201414307565-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

An integrated circuit layout is formed by performing a routing step forming a routing layout of routing conductors and routing connection vias prior to performing a power grid connection step which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.

First claim

I claim:

1. A method of forming a layout of an integrated circuit having:
a plurality of standard cells connected to draw power from standard-cell power conductors in a standard-cell conductor layer; and
a plurality of power grid conductors disposed overlapping at least portions of said plurality standard-cell power conductors in a further layer separate from said standard-cell conductor layer, said method comprising the steps of:
forming a power grid layout placing said plurality of power grid conductors in said integrated circuit;
subsequent to said forming a power grid layout step, a routing step forming a routing layout of routing conductors and routing connection vias to connect different portions of said plurality of standard cells; and
subsequent to said routing step, a power grid connection step forming a power connection via layout of power connection vias to connect said plurality of power grid conductors to said plurality of standard-cell power conductors, wherein
said power grid connection step is responsive to positions of said routing connection vias determined in said routing step to position said power grid connection vias at positions meeting a minimum via spacing requirement from said routing connection vias.

2. A method as claimed in claim 1 , wherein said routing conductors are in said further layer.

3. A method as claimed claim 1 , wherein said routing conductors are formed at positions meeting a minimum conductor spacing requirement from other conductors.

4. A method as claimed in claim 3 , wherein said minimum conductor spacing requirement is less than said minimum via spacing requirement.

5. A method as claim in claim 1 , wherein said plurality of routing conductors comprise a plurality of substantially parallel linear routing conductors.

6. A method as claimed in claim 5 , wherein said plurality of power grid conductors comprise a plurality of substantially parallel linear power grid conductors disposed substantially parallel with said plurality of substantially parallel linear routing conductors.

7. A method as claimed in claim 6 , wherein said plurality of standard-cell power conductors comprise a plurality of substantially parallel linear standard cell power conductors disposed substantially parallel with and overlapped by said plurality of substantially parallel linear power grid conductors with said further layer one metal layer above said plurality of substantially parallel linear standard-cell power conductors.

8. A method as claimed in claim 1 , wherein said standard-cell conductor layer is a metal one layer of said integrated circuit.

9. A method as claimed in claim 8 , wherein said further layer is a metal two layer of said integrated circuit.

10. A method as claimed in claim 1 , wherein said plurality of standard cells comprise said standard-cell power conductors.

11. A method as claimed in claim 1 , comprising, prior to said routing step, forming a standard-cell layout placing said plurality of standard cells in said integrated circuit.

12. A method as claimed in claim 1 , wherein a further minimum via spacing requirement applies to spacing between power grid connection vias.

13. A method as claimed in claim 1 , comprising storing computer readable data specifying said routing layout and said power connection via layout for use in manufacture of said integrated circuit including said routing layout and said power connection via layout.

14. A method as claimed in claim 13 , comprising using said computer readable data to control forming one or more masks for manufacturing said integrated circuit including said routing layout and said power connection via layout.

15. A non-transitory computer readable storage medium storing a computer program for controlling a computer to perform a method as claimed in claim 1 .

Assignees

• Advanced Risc Mach Ltd

Inventors

• Frederick Jr Marlin Wayne

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title