Sub word line driver of a semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9543306-B1
Application number	US-201514958432-A
Country	US
Kind code	B1
Filing date	Dec 3, 2015
Priority date	Jun 30, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including an active region extended in a first direction; a plurality of gate electrodes extended in a second direction perpendicular to the active region; first and second metal contacts formed over the active region between the gate electrodes; a plurality of metal pads coupled to the first metal contacts; and a plurality of metal signal lines coupled to the second metal contacts, extended in the second direction, and bent at specific parts adjacent to the metal pads.

First claim

What is claimed is:

1. A sub word line driver of a semiconductor memory device comprising:
a semiconductor substrate including a PMOS region and a NMOS region, wherein an active region is formed to extend in a first direction in the PMOS section;
a first metal contact formed over an edge of the active region;
a second metal contact formed over a middle of the active region;
a gate electrode extended in a second direction perpendicular to the first direction, and formed to include a hole through which a part of the active region is exposed;
a metal pad formed over the first metal contact and coupled to the first metal contact; and
a metal signal line coupled to the second metal contact, extended in the second direction, and bent in the first direction at a specific part adjacent to the metal pad,
wherein the second metal contact is formed over the exposed active region inside the hole of the gate electrode with a gap between the second metal contact and the Rate electrode,
wherein the sub word line driver is repeatedly arranged in the first direction, and
wherein the bent part of the metal signal line of the sub word line driver is arranged to overlap with a first adjacent sub word line driver, and the bent part of the metal signal line of a second adjacent sub word line driver is arranged to overlap with the sub word line driver such that an upper portion of the gap in the first direction has substantially a same size as a lower portion of the gap in the first direction.

2. The sub word line driver of claim 1 , wherein the sub word line driver is arranged between a plurality of cell regions of the semiconductor memory device.

3. The sub word line driver of claim 1 , further comprising a PMOS transistor region and a NMOS transistor region.

4. The sub word line driver of claim 3 , wherein a critical dimension of the gate electrode arranged in the PMOS transistor region is larger in size than a critical dimension of the gate electrode arranged in the NMOS transistor region.

5. The sub word line driver of claim 1 , wherein one or more of the metal signal lines arranged at an outermost part of an upper portion of the sub word line driver are bent along upper outer walls of the metal pads, and one or more of the metal signal lines arranged at an outermost part of an lower portion of the sub word line driver are bent along lower outer walls of the metal pads.

Assignees

• Sk Hynix Inc

Inventors

• Lee Han Kyu

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• H01L29/42356

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic

• H01L27/105 Primary

  Electricity · mapped topic