Chip to chip interconnect in encapsulant of molded semiconductor package

Patent metadata

Field	Value
Publication number	US-11133281-B2
Application number	US-201916375479-A
Country	US
Kind code	B2
Filing date	Apr 4, 2019
Priority date	Apr 4, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

First claim

What is claimed is:

1. A method of forming a packaged semiconductor device, comprising:
providing a first semiconductor die that comprises a main surface with a first conductive pad;
providing a second semiconductor die that comprises a main surface with a second conductive pad;
arranging the first and second semiconductor dies such that the second semiconductor die is disposed laterally side by side with the first semiconductor die and forming an encapsulant body around the first and second semiconductor dies such that the main surfaces of the first and second semiconductor dies are each disposed below an upper surface of the encapsulant body;
forming a first conductive track in the upper surface of the encapsulant body that electrically connects the first conductive pad to the second conductive pad;
forming a protective layer over the first conductive track; and
wherein the encapsulant body comprises a laser activatable mold compound; and
wherein the first conductive track is formed in a first laser activated region of the laser activatable mold compound,
wherein the protective layer comprises an electrically insulating material different from the laser activatable mold compound,
wherein the protective layer contacts and completely covers an upper surface of the first conductive track.

2. The method of claim 1 , wherein forming the first conductive track comprises:
directing a laser on the laser activatable mold compound thereby forming the first laser activated region; and
performing a plating process that forms conductive material in the first laser activated region.

3. The method of claim 2 , wherein the plating process is an electroless liquid plating process.

4. The method of claim 1 , further comprising:
providing a first vertical interconnect structure on the first conductive pad before the encapsulating;
providing a second vertical interconnect structure on the second conductive pad before the encapsulating,
wherein the encapsulating covers the first and second conductive pads with material of the encapsulant body, and
wherein after the encapsulating, outer ends of the first and second vertical interconnect structures are exposed at the upper surface of the encapsulant body.

5. The method of claim 4 , wherein the encapsulating of the first and second semiconductor dies comprises completely covering the first vertical interconnect structures with material of the encapsulant body, and wherein the method further comprises performing a thinning process after the encapsulating, and wherein the thinning process removes material from the upper surface of the encapsulant body until the outer ends of the first and second vertical interconnect structures are exposed from the encapsulant body.

6. The method of claim 4 , wherein encapsulating the first and second semiconductor dies comprises an injection molding process, and wherein the injection molding process comprises using an injection cavity that is dimensioned to cover the main surfaces of the first and second semiconductor chips with liquified molding material while exposing the outer ends of the first and second vertical interconnect structures from the liquified molding material.

7. The method of claim 4 , wherein the first conductive track is formed to directly connect with the outer ends of the first and second vertical interconnect structures.

8. The method of claim 1 , further comprising:
providing a die paddle with a plurality of electrically conductive leads extending away from the die paddle;
attaching a lower surface of the first semiconductor die that is opposite from the main surface of the first semiconductor die to a first lateral region of the die paddle;
attaching a lower surface of the second semiconductor die that is opposite from the main surface of the second semiconductor die to a second lateral region of the die paddle that is laterally adjacent to the first lateral region, and
wherein the upper surface of the encapsulant body is disposed over the die paddle,
wherein after forming the protective layer the first conductive track is electrically isolated from each of the leads in the plurality.

9. The method of claim 1 , wherein the first semiconductor die further comprises a third conductive pad disposed on the main surface of the first semiconductor die, wherein the second semiconductor die further comprises a fourth conductive pad disposed on the main surface of the second semiconductor die, wherein the method further comprises forming a second conductive track in the upper surface of the encapsulant body that electrically connects the third conductive pad to the fourth conductive pad, and wherein after forming the protective layer the first and second conductive tracks are configured as independent electrical nodes of the packaged semiconductor device.

10. The method of claim 9 , wherein the first conductive track comprises a first elongated span that extends in a first direction, wherein the second conductive track comprises a second elongated span that extends in a second direction, and wherein the second direction is non-parallel to the first direction.

Assignees

• Infineon Technologies Ag

Inventors

• Saw Khay Chwan
• Chiang Chau Fatt
• Macheiner Stefan
• Yong Wae Chet

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/40

  characterised by their materials · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title

• H10W72/222

  Multilayered bumps, e.g. a coating on top and side surfaces of a bump core · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title