Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking

Patent metadata

Field	Value
Publication number	US-11133206-B2
Application number	US-201916528099-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Apr 15, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

First claim

The invention claimed is:

1. A method of marking a substrate, the method comprising:
forming a layer of photoresist on a substrate;
projecting a first pattern of actinic radiation onto the layer of photoresist using a mask-based photolithography system, the first pattern defining semiconductor device structures;
projecting a second pattern of actinic radiation onto the layer of photoresist using a direct-write projection system, the second pattern defining a unique wiring structure having a unique electrical signature and related to unique marking of the substrate;
developing the layer of photoresist to generate a relief pattern; and
forming the unique wiring structure having the unique electrical signature.

2. The method of claim 1 , wherein the unique wiring structure is an electrical line.

3. The method of claim 1 , further comprising varying electrical resistance of the unique wiring structure from die to die by varying shape of the unique wiring structure.

4. The method of claim 1 , wherein a shape of the unique wiring structure is varied by varying at least one of line length, line width, line path, line turns, and line cross-sectional area.

5. The method of claim 1 , wherein the unique wiring structure is a matrix of conductive paths, wherein each conductive path is varied in geometry providing one of multiple electrical resistance values.

6. The method of claim 1 , wherein the unique electrical signature includes a unique resistance or capacitance value.

7. The method of claim 1 , wherein the unique wiring structure is positioned on a corresponding die at a location separated from die circuitry.

8. The method of claim 1 , wherein placement of blocks on conductive paths is varied by coordinate location to define different graphical arrangements of the unique wiring structure.

9. The method of claim 1 , wherein the first pattern is projected subsequent to projecting the second pattern.

10. The method of claim 1 , wherein the second pattern is projected subsequent to projecting the first pattern.

11. The method of claim 1 , wherein the unique wiring structure represents a serial number or date of manufacture, chip specifications, or generation of technology.

Assignees

• Tokyo Electron Ltd

Inventors

• Fulford H Jim
• Schepis Anthony
• Devilliers Anton J

Classifications

• H10W46/401

  for identification or tracking · CPC title

• H10W46/103

  alphanumeric information, e.g. words, letters or serial numbers · CPC title

• H10P76/2042

  using lasers · CPC title

• H10W46/403

  for non-wireless electrical read out · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title