Method and system for die to wafer bonding
US-2026099099-A1 · Apr 9, 2026 · US
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Schepis Anthony patents
Schepis Anthony is listed as an inventor on 18 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Schepis Anthony |
| Total patents | 18 |
| First publication | Oct 15, 2020 |
| Latest publication | Apr 9, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus and method for wafer alignment
US-12512356-B2 · Dec 30, 2025 · US
Using laser based system for mean of shaping of unsingulated & singulated dies by substrate lattice manipulation
US-2025308902-A1 · Oct 2, 2025 · US
Die to wafer bonding method and apparatus with thermal contact die shape control
US-2025308949-A1 · Oct 2, 2025 · US
Die to wafer bonding method and apparatus with thermal contactless die shape control
US-2025308951-A1 · Oct 2, 2025 · US
3D multiple location compressing bonded arm for advanced integration
US-12381118-B2 · Aug 5, 2025 · US
Correcting of design and mask shape position due to die and wafer distortion for bonding
US-2025226265-A1 · Jul 10, 2025 · US
Method of patterning a substrate using a sidewall spacer etch mask
US-12099299-B2 · Sep 24, 2024 · US
Three-dimensional multiple location compressing bonded arm-poisedon 4 and poisedon 5 advanced integration
US-2024203797-A1 · Jun 20, 2024 · US
Apparatus and method for wafer alignment
US-2024203778-A1 · Jun 20, 2024 · US
Recent patents
Latest publications not already listed above.
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
US-11862497-B2 · Jan 2, 2024 · US
Method of patterning a substrate using a sidewall spacer etch mask
US-2023367217-A1 · Nov 16, 2023 · US
Method of patterning a substrate using a sidewall spacer etch mask
US-11782346-B2 · Oct 10, 2023 · US
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
US-2021351053-A1 · Nov 11, 2021 · US
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
US-11133206-B2 · Sep 28, 2021 · US
Patterning a substrate
US-2021088907-A1 · Mar 25, 2021 · US
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
US-2020328103-A1 · Oct 15, 2020 · US
Method for die-level unique authentication and serialization of semiconductor devices
US-2020328102-A1 · Oct 15, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 18 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W46/00 | 7 |
| H01L23/544 | 7 |
| H10W46/401 | 5 |
| H10W46/103 | 5 |
| H10P72/0618 | 5 |