Semiconductor device with authentication code

Patent metadata

Field	Value
Publication number	US-9502405-B1
Application number	US-201514837707-A
Country	US
Kind code	B1
Filing date	Aug 27, 2015
Priority date	Aug 27, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches. Devices are formed from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective. One or more measurements are performed to determine which devices are defective and which devices are not defective. The results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed. Advantageously, the unique authentication code represents a physically unclonable function.

First claim

What is claimed is:

1. A method comprising steps of:
forming a plurality of contact trenches in a semiconductor structure, wherein the plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches;
forming devices from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective; and
measuring which devices are defective and which devices are not defective;
wherein the results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed.

2. The method of claim 1 , wherein the devices are field effect transistors.

3. The method of claim 2 , wherein the plurality of contact trenches are used to form one or more of drain contacts, source contacts, and gate contacts of the field effect transistors.

4. The method of claim 3 , wherein for a given field effect transistor that is defective, at least one of the contact trenches respectively associated with a drain contact, a source contact, and a gate contact is improperly formed such that the at least one improperly formed contact trench causes the respective contact to fail to conductively connect with a corresponding active region of the given field effect transistor.

5. The method of claim 1 , wherein the step of forming a plurality of contact trenches in a semiconductor structure further comprises:
forming a mask having contact openings, wherein each contact opening has a width selected to result in improper contact trench formation in a random number of the plurality of contact trenches; and
etching the plurality of contact trenches through the contact openings in the mask.

6. The method of claim 5 , wherein, under a first process variation, the etching step forms contact trenches at a first depth that enables conductive connection between a contact and a corresponding active region.

7. The method of claim 6 , wherein, under a second process variation, the etching step forms contact trenches at a second depth that fails to enable conductive connection between a contact and a corresponding active region.

8. The method of claim 7 , wherein the second process variation is at least caused by a variation in a lithographic process.

9. The method of claim 7 , wherein the second process variation is at least caused by a variation in the etching step.

10. The method of claim 1 , wherein the unique authentication code represents a physically unclonable function.

11. A method comprising steps of:
forming a plurality of field effect transistor devices in an integrated circuit, wherein the plurality of field effect transistor devices are formed with a set of contact trenches with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches;
applying gate voltage to the plurality of devices; and
determining which devices conduct drain to source current, and which devices fail to conduct drain to source current due to at least one improperly formed contact trench; and
identifying a unique authentication code for the integrated circuit based on the determination step.

12. The method of claim 11 , wherein for a given field effect transistor device that fails to conduct drain to source current, at least one of the contact trenches respectively associated with a drain contact and a source contact is improperly formed during the device forming step.

13. The method of claim 11 , wherein the set of contact trenches are formed by:
forming a mask having contact openings, wherein each contact opening has a width selected to result in improper contact trench formation in a random number of the set of contact trenches; and
etching the set of contact trenches through the contact openings in the mask.

14. The method of claim 11 , wherein the unique authentication code represents a physically unclonable function.

15. An integrated circuit, comprising:
a plurality of field effect transistor devices; wherein the plurality of field effect transistors are formed with a set of contact trenches with a contact opening width selected to result in improper contact trench formation in a random number of the set of contact trenches such that devices formed with the improperly formed contact trenches are defective;
wherein the defective field effect transistor devices form a unique authentication code for the integrated circuit.

16. The integrated circuit of claim 15 , wherein the set of contact trenches are used to form one or more of drain contacts, source contacts, and gate contacts of the field effect transistor devices.

17. The integrated circuit of claim 16 , wherein for a given field effect transistor device that is defective, at least one of the contact trenches respectively associated with a drain contact, a source contact, and a gate contact is improperly formed such that the at least one improperly formed contact trench causes the respective contact to fail to conductively connect with a corresponding active region of the given field effect transistor device.

18. The integrated circuit of claim 15 , wherein forming the set of contact trenches further comprises: forming a mask having contact openings, wherein each contact opening has a width selected to result in improper contact trench formation in a random number of the set of contact trenches; and etching the set of contact trenches through the contact openings in the mask.

19. The integrated circuit of claim 18 , wherein, under a first process variation, the etching step forms contact trenches at a first depth that enables conductive connection between a contact and a corresponding active region.

20. The integrated circuit of claim 19 , wherein, under a second process variation, the etching step forms contact trenches at a second depth that fails to enable conductive connection between a contact and a corresponding active region.

Assignees

• IBM

Inventors

• Cao Qing
• Cheng Kangguo
• Li Zhengwen
• Liu Fei

Classifications

• H10W46/601

  for use after dicing · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title