Devices and methods for detecting counterfeit semiconductor devices

US9941223B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9941223-B2
Application numberUS-201514821160-A
CountryUS
Kind codeB2
Filing dateAug 7, 2015
Priority dateAug 8, 2014
Publication dateApr 10, 2018
Grant dateApr 10, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques for providing a tamper mechanism for semiconductor devices are disclosed herein. The techniques include, for example, providing at least one die and at least one strain gauge, orienting the at least one strain gauge to the die, forming an encapsulated semiconductor device by encapsulating the die and each strain gauge within a mold compound to maintain respective orientation, and measuring an initial strain value for the at least one strain gauge after forming the encapsulated semiconductor device.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for providing a tamper mechanism for semiconductor devices, the method comprising: providing at least one die and at least one strain gauge; orienting the at least one strain gauge relative to the at least one die; forming an encapsulated semiconductor device by encapsulating the at least one die and the at least one strain gauge within a mold compound to maintain respective orientation of the die and each strain gauge; measuring an initial strain value of the at least one strain gauge after forming the encapsulated semiconductor device; and adjusting the strain value for each strain gauge to account for shelf-time post manufacturing. 2. The method of claim 1 , further comprising: storing the at least one initial strain value in a memory of the die. 3. The method of claim 2 , further comprising: storing a tolerance range for the at least one initial strain value in the memory of the die. 4. The method of claim 3 , further comprising: measuring a subsequent strain value for the at least one strain gauge; and comparing the subsequent strain value to the initial strain value; and determining the encapsulated semiconductor device is compromised when the subsequent strain value is outside the tolerance of the initial strain value. 5. The method of claim 1 , further comprising: wirelessly communicating, by each strain gauge, the initial strain value for each respective strain gauge to the die to cause the die to store the initial strain value for each respective strain gauge in a memory. 6. The method of claim 1 , further comprising: electrically communicating, by each strain gauge, the initial strain value for each respective strain gauge to the die to cause the die to store the initial strain value for each respective strain gauge in a memory. 7. The method of claim 1 , further comprising: providing a memory in communication with the at least one strain gauge; communicating, by each strain gauge, the initial strain value for each respective strain gauge to the memory to cause the memory to store the initial strain value for each respective strain gauge. 8. The method of claim 1 , wherein the step for orienting the at least one strain gauge on the substrate further comprises: mounting each strain gauge to at least a portion of the die. 9. The method of claim 1 , further comprising: integrally forming the at least one strain gauge as part of the die. 10. The method of claim 1 , wherein the at least one strain gauge comprises at least two strain gauges, the method further comprising: minimizing common mode variation using strain values measured at each of the at least two strain gauges. 11. The method of claim 1 , wherein the strain gauge is a silicon based strain gauge. 12. The method of claim 11 , wherein the strain gauge is a piezoresistive silicon strain gauge. 13. The method of claim 1 , wherein the at least one strain gauge comprises two strain gauges. 14. A semiconductor device that measures strain from tampering, the device comprising: at least one die; at least one strain gauge, the die and the strain gauge being encapsulated in a mold compound, the strain gauge for measuring strain induced on the mold compound communication interfaces operatively coupled to the at least one strain gauge and configured to transmit a strain value for each strain gauge, wherein the strain value has a value that accounts for shelf-time post manufacturing; and a memory operatively coupled to the communication interfaces and configured to store the strain value for each strain gauge, wherein the communication interfaces and the memory are operatively coupled to the die, wherein the die is configured to receive the strain value for each strain gauge and cause the memory to store the strain value for each strain gauge, and wherein the memory is further configured to store a process executable by the die, the process when executed by the die, causes the die to: store at least an initial strain value for each strain gauge; and store one or more tolerance values corresponding to the initial strain value.

Assignees

Inventors

Classifications

  • H10W42/405Primary

    using active circuits · CPC title

  • by measuring the permanent deformation of gauges, e.g. of compressed bodies · CPC title

  • using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material · CPC title

  • H01L23/576Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9941223B2 cover?
Techniques for providing a tamper mechanism for semiconductor devices are disclosed herein. The techniques include, for example, providing at least one die and at least one strain gauge, orienting the at least one strain gauge to the die, forming an encapsulated semiconductor device by encapsulating the die and each strain gauge within a mold compound to maintain respective orientation, and mea…
Who is the assignee on this patent?
Charles Stark Draper Laboratory Inc
What technology area does this patent fall under?
Primary CPC classification H10W42/405. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).