FinFET having locally higher fin-to-fin pitch

Patent metadata

Field	Value
Publication number	US-11114435-B2
Application number	US-201615382376-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2015
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

First claim

What is claimed is:

1. A semiconductor fin device comprising:
at least three fins including first to third fins protruding from a substrate and arranged to extend in parallel in a first direction and further arranged to laterally alternate in a second direction with a plurality of shallow trench isolation structures, wherein each of the at least three fins is separated from an immediately adjacent one of the at least three fins by a first fin spacing and by one of the shallow trench isolation structures, and wherein immediately adjacent ones of the shallow trench isolation structures are discretely separated from each other in the second direction by one of the at least three fins,
wherein at least a portion of each of the first fin and the second fin of the at least three fins vertically protrudes to substantially the same vertical level higher than upper surfaces of the shallow trench isolation structures immediately adjacent to a respective one of the each of the first fin and the second fin, and
wherein the third fin is formed laterally between the first fin and the second fin in the second direction, the third fin having a non-protruding region which extends vertically to a level below or equal to upper surfaces of the shallow trench isolation structures immediately adjacent to the third fin; and
a first gate dielectric that is conformal with respect to topmost surfaces and upper sidewall portions of the first and second fins,
wherein the first gate dielectric has the same composition at portions contacting each of the first, second and third fins,
wherein the first gate dielectric overlaps and contacts a topmost portion of the third fin in the non-protruding region and immediately adjacent ones of the shallow trench isolation structures with respect to the third fin, and wherein the first gate dielectric contacting sidewalls of the first fin and sidewalls of the second fin has a thickness measured in the second direction that is at least half of the first fin spacing.

2. The semiconductor fin device according to claim 1 , wherein the semiconductor fin device is a fin field effect transistor (finFET) further comprising a source and a drain, wherein the source and the drain are laterally spaced from each other by the first gate dielectric.

3. The semiconductor fin device according to claim 2 , wherein regions of the third fin outside the non-protruding region comprise one or both of a further source connected to the source and a further drain connected to the drain.

4. A semiconductor circuit comprising the semiconductor fin device according to claim 1 and further comprising a second fin device, the second fin device comprising:
at least two fins arranged to extend in parallel in the first direction and laterally separated from each other in the second direction by second shallow trench isolation structures having the first fin spacing, the at least two fins protruding out from the substrate to a vertical level higher than the upper surface of the second shallow trench isolation structures; and
a conformal second gate dielectric on and covering at least part of two of the at least two fins.

5. The semiconductor circuit according to claim 4 , wherein the thickness of the second gate dielectric is smaller than half of the first fin spacing.

6. The semiconductor circuit according to claim 4 , wherein the semiconductor first fin device and the second fin device are fin field effect transistors.

7. The semiconductor fin device according to claim 1 , wherein the first gate dielectric is a single layer gate dielectric.

8. The semiconductor fin device according to claim 1 , wherein the first gate dielectric is a dual layer gate dielectric.

9. The semiconductor fin device according to claim 1 , wherein the non-protruding region of the third fin extends vertically to a level below the upper surfaces of the shallow trench isolation structures immediately adjacent to the third fin.

10. The semiconductor fin device according to claim 2 , wherein the finFET is a high voltage finFET.

11. The semiconductor fin device according to claim 10 , wherein an operational voltage of the finFET is at least 1V.

12. A semiconductor fin device comprising:
at least three fins including first to third fins protruding from a substrate and arranged to extend in parallel in a first direction and further arranged to laterally alternate in a second direction with a plurality of shallow trench isolation structures, wherein each of the at least three fins is separated from an immediately adjacent one of the at least three fins by a first fin spacing and by one of the shallow trench isolation structures, and wherein immediately adjacent ones of the shallow trench isolation structures are discretely separated from each other in the second direction by one of the at least three fins,
wherein at least a portion of each of the first fin and the second fin of the at least three fins vertically protrudes to substantially the same vertical level higher than upper surfaces of the shallow trench isolation structures immediately adjacent to a respective one of the each of the first fin and the second fin, and
wherein the third fin is formed laterally between the first fin and the second fin in the second direction, the third fin having a non-protruding region which extends vertically to a level below or equal to upper surfaces of the shallow trench isolation structures immediately adjacent to the third fin; and
a first gate dielectric that is conformal with respect to topmost surfaces and upper sidewall portions of the first and second fins,
wherein the first gate dielectric has the same composition at portions contacting each of the first, second and third fins, and
wherein the at least three fins comprise a plurality of third fins including the third fin, wherein each of the third fins is formed laterally between the first fin and the second fin in the second direction, and wherein each of the third fins has a respective non-protruding region which extends vertically to a level below or equal to upper surfaces of the shallow trench isolation structures immediately adjacent to a respective one of the third fins.

13. The semiconductor fin device according to claim 12 , wherein the third fins are consecutively arranged in the second direction between the first fin and the second fin.

14. A method of fabricating a semiconductor fin device, the method comprising:
forming at least three fins including first to third fins protruding from a substrate and arranged to extend in parallel in a first direction and further arranged to laterally alternate in a second direction with a plurality of shallow trench isolation structures, wherein each of the at least three fins is separated from an immediately adjacent one of the at least three fins by a first fin spacing and by one of the shallow trench isolation structures, and wherein immediately adjacent ones of the shallow trench isolation structures are discretely separated from each other in the second direction by one of the at least three fins,
wherein forming the at least three fins comprises forming the first fin and the second fin such that at least a portion of each of the first fin and the second fin vertically protrudes to substantially the same vertical level higher than upper surfaces of the shallow trench isolation structures immediately adjacent to a respective one of the each of the first fin and the second fin,
wherein forming the at least three fins further comprises forming the third fin laterally between the first and the second fin in the second direction, and
selectively removing at least a portion of the third fin su

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Hellings Geert
• Boschke Roman
• Linten Dimitri
• Horiguchi Naoto

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title