Semiconductor device and method
US-2024395867-A1 · Nov 28, 2024 · US
US8993399B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993399-B2 |
| Application number | US-201313896930-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 17, 2013 |
| Priority date | May 17, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.
Opening claim text (preview).
What is claimed is: 1. A method comprising: obtaining a structure comprising a bulk silicon substrate, an epitaxial layer comprising carbon doped silicon on the substrate, an epitaxial layer containing germanium on the carbon doped silicon layer, and a layer comprising crystalline silicon on the epitaxial layer containing germanium; forming an isolation region on the structure electrically isolating a first region of the structure from a second region of the structure; removin…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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