Contact-first field-effect transistors

Patent metadata

Field	Value
Publication number	US-11101367-B2
Application number	US-201916670894-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Jun 19, 2015
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A method for forming a device structure provides for forming a fin of a semiconductor material. A first contact is formed on the fin. A second contact is formed on the fin and spaced along a length of the fin from the first contact. A self-aligned gate electrode is formed on the fin that is positioned along the length of the fin between the first contact and the second contact.

First claim

What is claimed is:

1. A method for forming a device structure, the method comprising:
forming a fin comprised of a semiconductor material;
forming a first contact on the fin;
forming a second contact on the fin and spaced along a length of the fin from the first contact;
forming a self-aligned gate electrode on the fin that is positioned along the length of the fin between the first contact and the second contact; and
for each contact on the fin:
forming a dielectric spacer between the self-aligned gate electrode and the contact; and
forming a source/drain region by doping a portion of the fin with dopant from the dielectric spacer.

2. The method of claim 1 further comprising:
forming a first dielectric spacer between the first contact and the self-aligned gate electrode,
wherein gate lithography is eliminated based on forming the self-aligned gate electrode between the first contact and the second contact via self-alignment.

3. The method of claim 2 , further comprising:
forming a second dielectric spacer between the second contact and the self-aligned gate electrode.

4. The method of claim 3 , wherein the first dielectric spacer and the second dielectric spacer each include a dopant providing a solid-state diffusion source, and comprising:
doping a first portion of the fin with the dopant from the first dielectric spacer to define a first source/drain region; and
doping a second portion of the fin with the dopant from the second dielectric spacer to define a second source/drain region.

5. The method of claim 2 , further comprising:
removing the first dielectric spacer; and
forming a second dielectric spacer between the first contact and the self-aligned gate electrode.

6. The method of claim 5 , wherein the first dielectric spacer is comprised of a first dielectric material having a first relative permittivity, and the first dielectric spacer is comprised of a second dielectric material having a second relative permittivity less than the first relative permittivity.

7. The method of claim 1 , wherein the first contact and the second contact each include a first layer comprised of a first material and a second layer comprised of a second material.

8. The method of claim 7 , wherein the first material comprises a dopant providing a solid-state diffusion source, and comprising:
doping a first portion of the fin with the dopant from the first material of the first contact to define a first source/drain region; and
doping a second portion of the fin with the dopant from the first material of the second contact to define a second source/drain region.

9. The method of claim 1 , wherein the first contact has a top surface, and the self-aligned gate electrode has a top surface that is recessed below the top surface of the self-aligned gate electrode to define a cavity between the first contact and the second contact.

10. The method of claim 9 , further comprising:
forming a dielectric layer in the cavity between the first contact and the second contact.

11. A method for forming a fin-type field effect transistor device structure, the method comprising:
forming a fin comprised of a semiconductor material;
forming a first contact that partially wraps around a first end of the fin;
forming a second contact that partially wraps around a second end of the fin and spaced along a length of the fin from the first contact;
forming a self-aligned gate electrode on the fin that is positioned along the length of the fin between the first contact and the second contact; and
for each contact on the fin:
forming a dielectric spacer between the self-aligned gate electrode and the contact; and

forming a source/drain region by doping a portion of the fin with dopant from the dielectric spacer.

12. The method of claim 11 , further comprising:
forming a first dielectric spacer between the first contact and the self-aligned gate electrode,
wherein gate lithography is eliminated based on forming the self-aligned gate electrode between the first contact and the second contact via self-alignment.

13. The method of claim 12 , further comprising:
forming a second dielectric spacer between the second contact and the self-aligned gate electrode.

14. The method of claim 13 , wherein the first dielectric spacer and the second dielectric spacer each include a dopant providing a solid-state diffusion source, and comprising:
doping a first portion of the fin with the dopant from the first dielectric spacer to define a first source/drain region; and
doping a second portion of the fin with the dopant from the second dielectric spacer to define a second source/drain region.

15. The method of claim 12 , further comprising:
removing the first dielectric spacer; and
forming a second dielectric spacer between the first contact and the self-aligned gate electrode.

16. The method of claim 15 , wherein the first dielectric spacer is comprised of a first dielectric material having a first relative permittivity, and the first dielectric spacer is comprised of a second dielectric material having a second relative permittivity less than the first relative permittivity.

17. The method of claim 11 , wherein the first contact and the second contact each include a first layer comprised of a first material and a second layer comprised of a second material.

18. The method of claim 17 , wherein the first material comprises a dopant providing a solid-state diffusion source, and comprising:
doping a first portion of the fin with the dopant from the first material of the first contact to define a first source/drain region; and
doping a second portion of the fin with the dopant from the first material of the second contact to define a second source/drain region.

19. The method of claim 11 , wherein the first contact has a top surface, and the self-aligned gate electrode has a top surface that is recessed below the top surface of the self-aligned gate electrode to define a cavity between the first contact and the second contact.

20. The method of claim 19 , further comprising:
forming a dielectric layer in the cavity between the first contact and the second contact.

Assignees

• IBM

Inventors

• Hook Terence B
• Na Myung-Hee
• Pranatharthiharan Balasubramanian
• Scholze Andreas

Classifications

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title