Stacked nanowire

Patent metadata

Field	Value
Publication number	US-9252017-B2
Application number	US-201314044131-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	Sep 4, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.

First claim

What is claimed is:

1. A stacked nanowire device, comprising:
a fin etched from a substrate and formed on the substrate, the fin forming a vertical structure extending above the substrate, the fin including a first nanowire at a first location of the fin and a second nanowire at a second location of the fin, the first location and the second location being different locations at respective first vertical positions on the fin, and the fin also including oxidized portions formed at respective second vertical positions on the fin, different from the first vertical positions; and
at least two pairs of spacers, a first pair of spacers of the at least two pairs of spacers being arranged on opposite sides of the fin at the first location of the vertical structure of the fin and a second pair of the at least two pairs of spacers being arranged on the opposite sides of the fin at the second location of the vertical structure of the fin.

2. The device according to claim 1 , wherein the first location is vertically separated from the second location.

3. The device according to claim 1 , wherein the first nanowire and the second nanowire are formed through oxidation of the fin.

4. The device according to claim 1 , further comprising a dielectric film formed over the first pair of spacers of the at least two pairs of spacers.

5. The device according to claim 4 , wherein the second pair of spacers of the at least two pairs of spacers is formed on the dielectric film.

6. The device according to claim 5 , wherein a height of the dielectric film corresponds with a vertical separation between the first location and the second location.

7. The device according to claim 4 , wherein the first nanowire and the second nanowires are formed through oxidation of the structure including the dielectric film.

8. The device according to claim 1 , further comprising a hard mask formed above the fin.

9. The device according to claim 8 , further comprising a high density plasma oxide film structure formed on the hard mask.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title