Variable gate width for gate all-around transistors

Patent metadata

Field	Value
Publication number	US-9590089-B2
Application number	US-201113997162-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the plurality of vertically stacked nanowires formed of a same semiconductor material wherein one of the nanowires of the plurality of vertically stacked nanowires is an active nanowire and wherein one of the nanowires of the plurality of vertically stacked nanowires is an inactive nanowire, wherein the same semiconductor material of the inactive nanowire is severed in the channel region of the inactive nanowire;
a gate structure wrapped around the active nanowire, defining a channel region of the device; and
a source region and a drain region on opposite sides of the channel region.

2. The device of claim 1 ,
wherein the source region and the drain region are formed from a homogeneous material.

3. The device of claim 2 , wherein the homogeneous material is a single-crystalline semiconductor.

4. The device of claim 2 , wherein the homogeneous material is a metal.

5. The device of claim 1 , wherein the source region and the drain region are formed from a heterogeneous stack of semiconductor films.

6. The device of claim 1 ,
wherein the active nanowire has an active source portion within the source region of the device and
an active drain portion within the drain region of the device, and
wherein a metal source contact is wrapped around the active source portion and
a metal drain contact is wrapped around the active drain portion.

7. The device of claim 1 , wherein the same semiconductor material of the active nanowire and the inactive nanowire is silicon.

8. The device of claim 1 , wherein the same semiconductor material of the active nanowire and the inactive nanowire is germanium.

9. A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the plurality of vertically stacked nanowires formed of a same semiconductor material wherein one of the nanowires of the plurality of vertically stacked nanowires is an active nanowire and wherein one of the nanowires of the plurality of vertically stacked nanowires is an inactive nanowire;
a gate structure wrapped around the active nanowire, defining a channel region of the device; and
a source region and a drain region on opposite sides of the channel region wherein the same semiconductor material of the inactive nanowire is severed in the channel region of the inactive nanowire.

10. The device of claim 9 , wherein the source region and the drain region are formed from a homogeneous material.

11. The device of claim 10 , wherein the homogeneous material is a single-crystalline semiconductor.

12. The device of claim 10 , wherein the homogeneous material is a metal.

13. The device of claim 9 , wherein the source region and the drain region are formed from a heterogeneous stack of semiconductor films.

14. The device of claim 9 , wherein the active nanowire has an active source portion within the source region of the device and an active drain portion within the drain region of the device, and wherein a metal source contact is wrapped around the active source portion and a metal drain contact is wrapped around the active drain portion.

15. The device of claim 9 , wherein the same semiconductor material of the active nanowire and the inactive nanowire is silicon.

16. The device of claim 9 , wherein the same semiconductor material of the active nanowire and the inactive nanowire is germanium.

Assignees

• Rachmady Willy
• Le Van H
• Pillarisetty Ravi
• Kavalieros Jack T
• Chau Robert S
• Sung Seung Hoon
• Intel Corp

Inventors

• Rachmady Willy
• Le Van H
• Pillarisetty Ravi
• Kavalieros Jack T
• Chau Robert S
• Sung Seung Hoon

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L29/66613

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title