Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit

Patent metadata

Field	Value
Publication number	US-11101267-B2
Application number	US-201916444252-A
Country	US
Kind code	B2
Filing date	Jun 18, 2019
Priority date	Aug 10, 2018
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

First claim

What is claimed is:

1. An integrated circuit comprising:
at least one active region extending in a first row in a first direction, the at least one active region in the first row comprising a first active region extending in the first row in the first direction and a second active region extending in the first row in the first direction;
at least one active region extending in a second row in the first direction, the at least one active region in the second row comprising a third active region extending in the second row in the first direction and a fourth active region extending in the second row in the first direction; and
a multiple height cell comprising the at least one active region in the first row, the at least one active region in the second row, the first active region and the second active region extending in the first row in the first direction and respectively having a first conductivity type and a second conductivity type, the third active region and the fourth active region extending in the second row in the first direction and respectively having the first conductivity type and the second conductivity type, and at least one gate line extending in a second direction crossing the first direction,
wherein the first active region and the third active region are adjacent to each other, and
wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

2. The integrated circuit of claim 1 , wherein the diffusion break comprises a single diffusion break and a double diffusion break;
wherein the first active region and the third active region are each terminated by the double diffusion break, and
the second active region and the fourth active region are each terminated by the single diffusion break.

3. The integrated circuit of claim 1 , wherein the diffusion break comprises a single diffusion break and a double diffusion break;
wherein the first active region and the third active region are each terminated by the single diffusion break, and
the second active region and the fourth active region are each terminated by the double diffusion break.

4. The integrated circuit of claim 1 , wherein the multiple height cell comprises a contact that is connected to the first active region and the third active region and extends in the second direction through a boundary between the first row and the second row.

5. The integrated circuit of claim 1 , wherein the multiple height cell further comprises:
a power line extending in the first direction on a boundary between the first row and the second row; and
a via on the boundary between the first row and the second row and connected to the power line.

6. The integrated circuit of claim 1 , wherein the multiple height cell comprises:
at least one first conductive pattern formed on a first conductive layer; and
a second conductive pattern formed on a second conductive layer on the first conductive layer, wherein the second conductive pattern is configured to route an input signal or an output signal,
wherein the second conductive pattern extends in the second direction through a boundary between the first row and the second row.

7. The integrated circuit of claim 1 , wherein each of the at least one active region of the first row and the at least one active region of the second row is terminated by a single diffusion break or a double diffusion break based on a conductivity type of the active region.

8. The integrated circuit of claim 1 , further comprising:
cells placed in at least one row of the first row and the second row; and
wherein the multiple height cell is spaced apart from adjacent ones of the cells in the first direction by 1 Contacted Poly Pitch (CPP) or more.

9. The integrated circuit of claim 1 , wherein the multiple height cell comprises a plurality of transistor groups that are connected in parallel with each other and configured to commonly receive an input signal,
wherein each of at least two transistor groups from among the plurality of transistor groups includes transistors that share one gate line of the at least one gate line.

10. The integrated circuit of claim 1 , further comprising:
a single height cell that corresponds to an identical circuit as the multiple height cell and comprises at least one active region terminated by a diffusion break.

11. The integrated circuit of claim 10 , wherein the multiple height cell is configured to provide a higher operating speed than the single height cell.

12. The integrated circuit of claim 1 , wherein respective partial portions of the first active region and the third active region are connected to each other.

13. The integrated circuit of claim 12 , wherein the diffusion break comprises a double diffusion break; and
wherein the first active region and the third active region are terminated by the double diffusion break.

14. The integrated circuit of claim 12 , wherein the multiple height cell comprises a plurality of fins extending in the first direction,
wherein a number of fins overlapping the first active region or the third active region is greater than a number of fins overlapping the second active region or the fourth active region in a plane view of the integrated circuit.

15. The integrated circuit of claim 14 , wherein the multiple height cell comprises transistors that are connected in series to each other and formed in the first active region and the third active region.

16. An integrated circuit comprising:
a multiple height cell comprising a plurality of active regions in two or more rows and extending in a first direction,
wherein the multiple height cell comprises:
the plurality of active regions extending in the first direction and being terminated by a diffusion break;
at least one gate line extending in a second direction crossing the first direction; and
a plurality of transistor groups that are connected in parallel with each other and configured to commonly receive an input signal,
wherein each of at least two transistor groups from among the plurality of transistor groups includes transistors that share one gate line; and

a single height cell that corresponds to a circuit identical to the multiple height cell and comprises at least one active region terminated by the diffusion break.

17. The integrated circuit of claim 16 , wherein the diffusion break comprises a single diffusion break and a double diffusion break; and
wherein each of the plurality of active regions is terminated by the single diffusion break or the double diffusion break based on a conductivity type of the active region.

18. The integrated circuit of claim 17 , wherein an active region for an N-channel field effect transistor (NFET) from among the plurality of active regions is terminated by the double diffusion break, and
wherein an active region for a P-channel field effect transistor (PFET) from among the plurality of active regions is terminated by the single diffusion break.

19. An integrated circuit comprising:
a multiple height cell comprising a plurality of active regions in two or more rows and extending in a first direction,
wherein the multiple height cell comprises:
the plurality of active regions extending in the first direction; and
at least one gate line extending in a second direction crossing the first direction,
wherein each of the plurality of active regions is terminated by a diffusion break;

cells placed in at least one row of the two or more rows; and
wherein the multiple

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jin-Young
• Park Jae-Ho
• Baek Sang-Hoon
• You Hyeon-Gyu
• Lee Dal-Hee

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D62/102 Primary

  Constructional design considerations for preventing surface leakage or controlling electric field concentration · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title